( ESNUG 360 Item 18 ) -------------------------------------------- [11/02/00]
From: Matt Gavin <mtgavin@collins.rockwell.com>
Subject: Customer DC Headaches w/ 0.01% Limitation on Fixing Violations
ESNUG gurus,
Could someone please give me a hand here...
I found the following (quoted below) on the solvNET site, in an article
(SYNTH-432604.html) dealing with fanout violations (titled "Problems with
huge fanout violations?"):
"According to SOLV-IT article STAR-36489, Design Compiler will not fix
design rule violations less than 0.01 percent."
Is this true? It might seem to expain why Synopsys is not fixing a handful
of hold time failures of about 0.017ns in my design (it is fixing many,
many others -- I have set the fix_hold attribute for all clocks.) Seems
quite strange that DC would have this limitation though.
FYI, I can't seem to find this reference to STAR-36489, anywhere on the
SolvNET site.
Help!
- Matt Gavin
Rockwell Collins
( ESNUG 360 Networking Section ) --------------------------------- [11/02/00]
Nevada City, CA -- TDK Semiconductor seeks HDL-based engineers with DSP
experience. No headhunters, please. "Martin.Gravenstein@tsc.tdk.com"
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