( ESNUG 359 Item 1 ) --------------------------------------------- [9/13/00]
From: "Jay Adams" <Jay.Adams@marconi.com>
Subject: May God Help You If You Use The Synopsys Dual-Clock DW FIFO Parts
Hi, John,
You may be aware Synopsys admits 2 bugs in the DesignWare dual-clock FIFOs
and FIFO controller (DW_FIFO_S2_SF and DW_FIFOCTL_S2_SF.) Those are only
the beginning. Here are two additional features that they did not tell you
about:
1) When in the almost_empty state, the pop_ae flag can be deasserted at
any time there is a push, regardless of the number of words in the
FIFO. There is similar behavior for the half_full & almost_full flags.
2) When pushes and pops are occurring simultaneously, the empty state can
be mistakenly hit regardless of how many words are in the FIFO. Yes,
that's right, the empty state, and if your logic can't tolerate a
break in the data flow or you don't monitor the empty flag, then you're
screwed.
In other words, the flags on these Synopsys dual-clock DW FIFO parts are
useless.
I'm not going to explain the nuances of this behavior, I expect Synopsys to
do that and my time is needed to salvage the DISASTER that Synopsys has put
me in. I am writing this note because it is Synopsys's opinion that the
behavior designed above is as they designed it. Heres a summary of their
position:
"Yes, we are coming out with a new version on the next CD release
that doesn't exhibit these "qualities", but that is in no way is an
indication that we have done anything wrong in this component. Since
the FIFO is working as *we* have always intended it to, we do not
intend on informing the design community."
And heres one more bit of information. The FIFO model that they intend on
including in the next CD release will fix the above bugs, but only if the
depth is a power of 2. If its not a power of 2, then the bugs can still
occur! They claim that they will document this clearly. They also claimed
to me that bugs I listed are also documented in the current documentation.
So go read that and decide for yourself what they mean by documentation.
So heres what I say to the design community: If you are using Synopsys's
dual-clock DesignWare FIFO controllers - May God be with you. This only
applies to the dual clock FIFO controllers, because I'm sure that everything
else in DesignWare is absolutely stable and that they are not holding any
"as designed" behaviors to themselves.
- Jay Adams, Manager, ASIC Design
Marconi Communications Warrendale, PA
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