( ESNUG 357 Item 8 ) --------------------------------------------- [8/10/00]
Subject: ( ESNUG 356 #5 ) Converting Xilinx/Altera Gates Into ASIC Gates
> I was just wandering if you know what the ratio of the newer FPGA gates to
> ASIC gates is? I have asked Xilinx but they couldn't tell me. I am new
> to the FPGA/ASIC process and am trying to come up to speed. Even a
> ballpark conversion ratio would be helpful.
>
> - Chris Frailey
> Motorola
From: Dave Chapman <dave@goldmountain.com>
John,
I'd start by saying that it depends on the vendor. For traditional Xilinx,
it you get 5-7% utilization, you did good (20:1 or 14:1 ratio.) For the
newer Xilinx, most Altera, and most other vendors, it's kind of hard to get
above 15% utilization (7:1 ratio).
I would expect these numbers to improve as place-&-route software improves,
but not by much. The problem is that the "macrocell" style of building
CPLDs and FPGAs does not lend itself to good automatic utilization.
Macrocells containing an ALU slice and all kinds of stuff frequently get
used as a 2-input MUX.
Actel claims that their ProAsic family gets much better utilization due to
its "tile" architecture, but your mileage may vary.
I have a simple metric: Find out how many bits of RAM can be built out of
the programmable logic sections (NOT the built-in RAM), and then multiply
by 6. That number is the real-world utilitzation you'll get. Note that
this method produces numbers which are a lot lower that the numbers in the
colorful brochure.
Oh yeah, the "Buildable System" metric. It's _called_ B.S. Go figure.
- Dave Chapman Sonoma County, CA
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From: Tom Ayers <tomayers@believe.com>
John,
Here is some additional information on conversion factors.
The conversion factors will only work for random logic. Memories vary
greatly in size and implementation between different ASIC implementations
(differential precharge discharge, single ended precharge discharge, single
ended minimum drive latch cell, standard cell latch array, standard cell
register array, etc) as well as differing greatly in FPGA implementation.
Here are some keys to remember:
1) Be careful about logic duplication. Many tools including Synplify for
synthesis and Xilinx Alliance for P&R can duplicate logic blocks either
to reduce net fanout or improve critical path speed. These factors can
change the conversion ratio in much the same way that compiling for
speed vs. area in Synopsys synthesis will do.
2) Memories should be handled one at a time. Both Xilinx and Altera
support special memory areas (block ram) on the die which can be used
for onchip memories but have width, depth restrictions and restrictions
on clocking and ports. Xilinx can also form memories out of CLB LUTs,
but Altera can not. At best, you can get 16bits of memory per LUT,
with approximately 6% additional overhead. Odd sizes has a minor effect
on the size, but additional ports have a dramatic effect as you would
expect.
Given this, the conversion ratios for Xilinx Virtex-E and Altera APEX 20K
random logic gates are approximately 5.3 and 4 respectively. We have not
seen a significant dependance on the type of logic implemented and given the
gate counts that these devices have statistics work in your favor. That is
to say that a Xilinx 2000E can get 378 Kgates and an APEX 20K 1500E can get
375 Kgates. You can do slightly better than this by minimizing logic
duplication if you do not care about running at speed. The best numbers are
4 for Xilinx and 3 for Altera.
Hope this helps.
- Thomas Ayers
Believe, Inc.
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