( ESNUG 357 Item 7 ) --------------------------------------------- [8/10/00]
Subject: ( ESNUG 356 #4 ) Synchronizers & Timing Problems With Reset Trees
> I have a reset net in my design. I am using "set_ideal_net" command in
> Design Compiler, but I still see huge SN/RN to Q/QN delays in my SDF file
> for any FF connected to the reset net. My design is hierarchical. Does
> anyone know how to take care of this problem?
>
> - Hooman Dadrassan
From: Wayne Miller <Wayne.A.Miller@smsc.com>
If I understand this correctly, you have a reset that drives a large load,
and you're running a pre-layout gate level simulation.
What you're seeing is correct.
"Ideal nets are networks of nets that are free from max_capacitance,
max_fanout, and max_transition design rule constraints. Ideal nets
are useful for reducing DRC violations caused by clock trees, because
these networks usually have high max_capacitance and max_fanout
violations."
But set_ideal_net doesn't change the physics of gate delays. When you
heavily load a buffer, its delay and transition time increases. If you need
to fix this in pre-layout sims, modify the propagation delay reported in
your SDF file for the buffer. Of course, this only makes sense if you're
going to buffer the net later in P&R.
Your other choice is to have Synopsys buffer the net for you. My AE has
been telling me there's some new buffering algorithm that does this nicely
for RESETs and SCAN_TEST_ENABLEs. (I haven't tried it yet.)
- Wayne Miller
Standard Microsystems Corporation Long Island, NY
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