( ESNUG 357 Item 2 ) --------------------------------------------- [8/10/00]
Subject: ( ESNUG 355 #5 )  Avanti Star-RC, EPIC Arcadia, Cadence Dracula

> That one anon review on parasitic extraction ( Item 46 in the DAC'00 Trip
> Report) was terrible!   I have to imagine that this person isn't active in
> the backend world --- too many strangely wrong comments and thoughts.
> Have someone who is in the backend read it, and they'll laugh or cry.  
>
>     - John Lee
>       Avanti                                     Fremont, CA


From: [ Engineer X ]

John,

The Avanti AE is correct; I do mostly front end.  I know a bit about layout,
but the last extraction stuff I did was when Cadence Dracula was brand new.
I visited about 200 booths at DAC and reported on all of them to the best of
my limited abilities.  If he has specific corrections I would appreciate
them; I really want to know the scoop.  Politics say I must be anon.

    - [ Engineer X ]

         ----    ----    ----    ----    ----    ----   ----

From: John Lee <jolly@avanticorp.com>
To: [ Engineer X ]

I didn't mean to criticize you personally.  Your opinions were more factual
than my opinions would be about front-end products.  The extraction market
is fragmented, with about 5 major players -- Mentor (xCalibre), Synopsys
(Arcadia), Simplex (Fire&Ice), Frequency (Columbus) [Frequency is now known
as Sequence], and Avanti (Star-RC). 

Historically, Dracula has been the #1 parasitic extraction tool.  But about
5 years ago, Arcadia (from Epic then, now part of Synopsys) became the
market leader for "3D RC" extraction.

Recently (97, 98, 99), Star-RC has been the #1 RC extraction tool (according
to Dataquest, etc...)  Year 2000 looks like another winner for us, in an
even bigger way.

RC extraction, in some ways, is more of an engine -- kind of like delay
calculation.  It is a necessary technology.  However, integrated RC
extraction, like integrated delay calculation in a static timing analyzer,
is most important.  This is because "timing convergence" is so so important
for 0.18 micron and below physical design.  This is where integrated RC
extraction into a P&R tool, or integrated RC extraction with simulation (so
called "analysis" for power/timing/noise) are more important to users.

So rather than just compare accuracy/memory usage/runtime (which are
important), you should also see how well you can sign-off on
power/timing/noise, and how it fits in with your physical design tool.

This is really where Star-RC XT (XT is the high performance option) excels.
This is why the major ASIC vendors like LSI, TI, Lucent, Philips/VLSI, etc.
have chosen RCXT for their flows.  Or why the pure play foundries like TSMC,
UMC, CSM all have *purchased* RC for several years for their internal design
services.

Again, I'm really sorry for the rude message.  It wasn't intended as a knock
against you, but rather against unreviewed reviews in a "foreign" field!

    - John Lee
      Avanti                                     Fremont, CA

         ----    ----    ----    ----    ----    ----   ----

From: [ Engineer X ]
To: John Lee <jolly@avanticorp.com>

> Historically, Dracula has been the #1 parasitic extraction tool.  But
> about 5 years ago, Arcadia (from Epic then, now part of Synopsys) became
> the market leader for "3D RC" extraction.

Some engineers in my group benchmarked Arcadia and decided to stop using it
years ago.  The results were too flaky compared to Dracula.  On nets with
big differences, they couldn't justify Arcadia's numbers.  Hence no mention
in my review.


> RC extraction, in some ways, is more of an engine -- kind of like delay
> calculation.  It is a necessary technology.  However, integrated RC
> extraction, like integrated delay calculation in a static timing analyzer,
> is most important.  This is because "timing convergence" is so important
> for 0.18 micron and below physical design.  This is where integrated RC
> extraction into a P&R tool, or integrated RC extraction with simulation
> (so called "analysis" for power/timing/noise) are more important to users.
>
> So rather than just compare accuracy/memory usage/runtime (which are
> important), you should also see how well you can sign-off on
> power/timing/noise, and how it fits in with your physical design tool.

Good point! The image I have of Avanti is that your tools work really well
as long as they only talk to other Avanti tools.  My current customer, who
asked me to write my DAC report, is using Cadence P&R and Star-RC
extraction - life is not good.  My review assumed that this situation would
continue - incorrect for other users.


> This is really where Star-RC XT (XT is the high performance option)
> excels.  This is why the major ASIC vendors like LSI, TI, Lucent,
> Philips/VLSI, etc... have chosen RCXT for their flows.  Or why
> the pure play foundries like TSMC, UMC, CSM all have *purchased*
> RC for several years for their internal design services.

My impression is that RC has a big and generally satisfied customer base,
but XT was new and there really aren't a lot of testimonials yet.

    - [ Engineer X ]

         ----    ----    ----    ----    ----    ----   ----

From: John Lee <jolly@avanticorp.com>
To: [ Engineer X ]

Avanti Star-RC licensed the LEF/DEF interface from Cadence last year, so we
now have a neat, smooth flow with 3rd party P&R tools.  Some of our biggest
customers are running this flow.

Many of our Star-RC users have upgraded to Star-RC XT; our corporate web
site has some of the testimonials there.  It (XT) is worth checking out!
(Again, I apologize for the shameless plug).

If your customer is running a LEF/DEF flow, or similar cell based
methodology, RC XT should be an easy fit.

With respect to your comment on Arcadia, I think the biggest trouble that
users have, even today, is validating the accuracy claims from EDA vendors.
The most common way today to validate is to compare vs. Quickcap (also known
as Raphael-NES).  Quickcap is a great reference solver, and there are
automatic flows from "full-chip" extraction tools like Star-RC to generate
comparison data.  

    - John Lee
      Avanti                                     Fremont, CA

         ----    ----    ----    ----    ----    ----   ----

From: [ Engineer X ]
To: John Cooley <jcooley@world.std.com>

John (Cooley),

I may have been unclear about John Lee's response (or my limited
understanding of it).  His point is that for DSM designs, you get into this
cycle of (tweak netlist -> tweak placement -> tweak routing -> do
extraction -> STA -> tweak netlist) and the integration of the tools is
far more important than whether any single step is really the fastest/most
memory efficient tool available.  This is a damn good point.  The
interesting thing here is that all the major physical synthesis players
are going to a single binary database that all the tools connect to.  All
except Synopsys.  They do not yet have a detailed router, and their EPIC
backend tools have been languishing for years (they claim this will soon
change - we'll see).  The interesting thing is that they are the ones with
all the customer tape out stories.  Seems like either they are right in
their assertion that this backend cycle doesn't matter if your placement
is good enough, or they have attempted to do less than their competitors
and hence gotten a finished product earlier.  It will be interesting to
watch.

    - [ Engineer X ]

 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)