( ESNUG 352 Item 4 ) --------------------------------------------- [5/17/00]
Subject: ( ESNUG 351 #3 ) De-Glitching Coverage Tools Are A General Issue
> Unfortunately, I have not been able to turn "deglitch" off correctly and
> get a good run. And I don't have any time to work on it.
>
> My advice to others, especially if you are using Verilog-XL, or if you
> suspect you are getting false positives in combinatorial always@'s
> (always@(signal_list)), would be to run this code snippet: ...
>
> - Dan Joyce
> Compaq Computers
From: Dan Joyce
Hi, John,
I sent you the wrong test Verilog code snippet to test for that code
coverage bug in ESNUG 351 #3. Here's the correct version:
module test1(
);
reg clk;
reg [4:0] register;
reg [4:0] register_next_state;
reg error;
reg error_next_state;
reg [11:0] count;
initial begin
//$dumpvars;
register <= 0;
error <= 0;
clk <= 0;
count <= 0;
#20 clk <= 1;
end
always@(clk) clk <= #20 ~clk;
always@(posedge clk) begin
count <= count+1;
if (count == 12'hfff) $finish;
end
always@(register) begin
if(register[0]) register_next_state = 5'b00000;
else register_next_state = 5'b11111;
case(register)
5'b00000 : error_next_state = 0;
5'b11111 : error_next_state = 0;
default : error_next_state = 1; // This line should show NO
coverage!!!
endcase
end
always@(posedge clk) begin
register <= register_next_state;
error <= error_next_state;
end
endmodule
BTW, I think this bug is a generalized issue for all code coverage tools,
so your readers should try this test on their favorite coverage tool.
- Dan Joyce
Compaq Computers
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