( ESNUG 350 Item 3 ) --------------------------------------------- [4/27/00]
Subject: Scan Test Implications Of Clock Tree Synthesis Tools Like Ultima
> At the SNUG'00 vendor fair I saw a tool from Ultima called ClockWise.
> Caught my attention since Chip Architect and PhysOpt don't have this
> capability yet (but will soon). However, ClockWise claims to be able to
> use clock skew as an advantage, moving the clock edges to fix setup/hold
> times. Their idea both intrigues and scares the hell out of me. This
> would have very serious implications on hold violations on scan flops.
From: Willis Hendley <willis.hendley@east.sun.com>
Hi, John,
As silicon scales down farther below 0.18 um, we have to use localized skew.
This is because global clock skews with useful cycle times and hold
specifications won't be possible. Luckily scan flops can have increased
delay on their scan-data-in ports to handle mismatches between 'useful skew'
on the functional path and 'non-useful skew' with respect to the scan
inputs. The logic cone depth and wire delays driving scan-data-in is
typically much shallower than regular data inputs.
- Willis Hendley
Sun Microsystems Chelsmford, MA
|
|
