( ESNUG 349 Item 9 ) --------------------------------------------- [4/18/00]
Subject: ( ESNUG 343 #10 ) Fun Stuff We Found Analyzing Our .lib Files
> We always had the problems mentioned in this issue (unpredictable
> synthesis results per a library change). This is the first time we got
> some kind of a guide from the Israel Synopsys support team. It's a 10
> page article in SolvNet titled "DC Library Ultra Guidelines" (October
> 1999) and it has the detailed description of the new DC timing model, how
> to analyze a .lib, and plus basic library developer guidelines for their
> new timing model. It's Synthesis-625.html on SolvNet.
>
> A good, meaty guideline of library developing is sure missing.
>
> - Doron Nisenbaum
> Chip Express (Israel) Haifa, Israel
From: Dale Walter <dalew@actel.com>
Hi John,
We performed a study at Actel last summer to try to determine what cells
should be in an optimal synthesis library. Being an FPGA manufacturer,
Actel's libraries do not have as many cells as a typical ASIC library,
since we do not have multiple cells with different drive strengths. But
I believe the results of our study are analogous to the ASIC world.
In our study we chose to focus on the synergy between the cells that
exist in a library rather than their timing properties. Our libraries
make use of the simple linear timing model, which seems to yield fairly
accurate timing estimations for Actel architectures. The impetus for
this study was to determine which TMR (triple module redundancy)
flip-flops to develop for our Hi Rel customers. Rather than simply
making TMR equivalents of all existing regular flip-flops, we wanted to
determine the minimum set that would accomplish mapping yet still yield
the best QOR (quality of results).
As Doron Nisenbaum observed, Synopsys does not give much guidance in the
theory of library development. In previous libraries we simply threw
everything into the library that we had. We wondered if this was a good
idea, however, and wanted to find a way to empirically determine whether
a library was optimum.
We hired a college student for the summer to do all the grunt work. We
began with a simple library using the minimum set of cells for CMOS
technology library, as defined in the Synopsys Library Compiler User
Guide. This consisted of a 2-input AND gate, a 2-input OR gate, a
2-input NOR gate, and inverter, a D flip-flop with preset and clear, and
a D latch with preset and clear. The only thing left out was the
internal three-state buffer because none exist in any Actel antifuse
architecture. We used Synopsys' 99.05 release both for compiling the
libraries and synthesis.
Next we performed synthesis using the simple library on a suite of 23
designs. We tried to pick a diverse cross-section of large and
realistic designs, many of which were donated by customers. We measured
run time, area, and maximum delay in order to determine QOR.
After the first set of synthesis runs were completed, we began adding
cells to the simple library. We added just a few cells at a time and
then re-ran synthesis and took measurements. First we added some AND-OR
gates, then some NOR gates, AOI gates, XOR gates, OR-AND gates, etc.
Then we began adding enable flip-flops, MUX flip-flops, enable latches,
etc. In total we created 23 separate libraries. When all the tests
were completed, we plotted all the data on several graphs and analyzed
the results. We also took a detailed look at some of the designs to see
what DC was doing when we found blips on the graphs.
The results were quite interesting and in some cases surprising. With
the simple library, as might be expected, area was highest. Run times
and delays were also quite high. Area fell off quite steeply at first
as more cells were added, and then leveled off for the remainder of the
libraries. Adding enable flip-flops yielded the lowest area. Area
began to increase slightly as more cells were subsequently added.
Delays actually increased with the first four libraries, then steeply
fell with the next three, then leveled off asymptotically, gradually
decreasing in a step-wise fashion for the remainder of the libraries. A
few spikes were observed along the way which caused us to take a deeper
look at the synthesis results. To our surprise, we found that the
addition of certain cells caused chains of inverters to be added to some
paths, thus slowing them down. It should be noted that all cells in the
Actel MUX based antifuse architectures are implemented in silicon with
either a C-module (combinatorial), an S-module (sequential), or a
combination of the two. Thus all sequential cells have roughly the same
timing characteristics, as do all combinatorial cells. So we could not
find a good reason for DC adding the inverter chains.
Run times fell off steeply at first and then rose again, leveled off for
a short while, then slowly fell to their lowest level and stayed there
for awhile, then began to slowly rise again. The low level corresponded
to the addition of the more complex flip-flops and latches.
As a result of our study, we chose for an optimum library the one where
the area, delays, and run times all were at their lowest levels, making
sure to avoid any spikes. Although our method was very time-consuming,
it did give us a lot of confidence in our choice of cells, and has
subsequently been field proven. It has also opened our eyes to some
very scary gotchas which we may never otherwise have noticed. What we
are dealing with here is an extremely complicated beast. Although it
sounds like a good idea, I sincerely doubt that it is possible to
publish a meaty guideline for library development that could possibly
take into account all of the variables and the synergy between cells,
and I would be very skeptical of any that claimed to do so.
- Dale Walter
Actel Corp. Sunnyvale, CA
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