( ESNUG 349 Item 8 ) --------------------------------------------- [4/18/00]
Subject: Customer Pissed That Synopsys Recommended Custom Wire Load Models
> THE BIRDS & THE BEES: Currently, to manage the funky effects of hanging
> out around 0.25 um, chip designers use Design Compiler in conjunction with
> Wire Load Models. They're also using a class of tools which guesstimate
> physical effects (within 15 percent or so) that are best thought of as
> "planners". Their user stats:
>
> Avanti Planet-RTL ######## 17%
> Synopsys Chip Architect # 3%
> Synopsys FlexRoute 1%
>
> Once you're past the physical effects planning stage, there's another
> class of tools that manages physical effects via post-synthesis
> optimizations. Their SNUG'00 tool survey stats:
>
> Synopsys Floorplan Manager ########## 21%
> Avanti Saturn ###### 12%
> Cadence Phys Design Planner ## 5%
>
> Cadence PBopt should also be included here for completeness even though it
> wasn't in the survey. Anyway, the big problem is these Wire Load Model
> tools/approaches only work so-so, but they're as good as it gets for now.
From: [ BeetleJuice ]
John,
I'm pissed, but I must have no name here.
I have been consistently flabergasted at Synopsys's party line recommending
the use of Custom Wire Load Models. I see it all over their official DC
documentation and the Synopsys guys were talking about it at SNUG'00. The
idea is intellectually appealing, but the fact is they don't work and make
things worse. Considering that the wire load construction challenge is to
approximate a Poisson distribution with a single number, no matter what
number is chosen, it is going to be wrong.
The premise of Custom Wire Load models is that by mathematically removing
the highest and lowest values of the distribution (-trim) and drawing an
arbitrary line at a pre-determined percentage (-percentile), smoothing the
resulting table of numbers (-smooth), the resulting table will have far
greater predictive ability than the obviously conservative, sandbagged,
overly pessimistic tables supplied by those lowliest of leaches: the
semiconductor vendors.
As was pointed out by an astute user at the PhysOpt tutorial at Snug 2000
in San Jose, the values of the -trim and -percentile have more effect on
the value of the generated tables than the actual data set.
The default values of 10% trim and 50% percentile feed the delusion that
Vendor WLMs are overly conservative, because these unachievable numbers
make the design look much faster, and cannot be realized. A small detail,
usually discovered by the design team, in the 11th hour, under tremendous
time to market pressures.
Furthermore, as also pointed out at the PhysOpt tutorial, the tables for
custom WLMs are not populated above fanouts=19. Gee, what do you think
that happens on the clock, reset, scan, busses and any other nets that
might have fanouts greater than that?
To anyone contemplating the use of Custom WLMs, spend a bit of time
following the technique described by Steve Golson in his excellent paper at
last year's San Jose SNUG (I can't recall the title, but I do recall
it winning the best paper award.)
1.) Using Design Compiler, for a given block, generate timing endpoint
data with:
report_timing -path end -nosplit > filename.rpt
2.) Plot that curve with slack ratio on the X axis and aggregated path
on the Y axis (Sort the slack ratios to get a smooth curve).
3.) After doing this from the initial synthesis, do it again with the
post-placement parasitics, and overlay the curves.
4.) After generating the custom WLMs, retime the design with those WLMs.
Recall that the purpose of custom WLMs is to improve the predictive
quality of the synthesis results.
Look at these three plotted curves, and make sure that the Custom WLMs are
SIGNIFICANTLY better. I have done this and they were actually WORSE than
my vendor supplied models!
I cynically believe that the awful results that can be had using custom
WLMs is a Synopsys marketing ploy. "Gee, Custom WLMs did not solve your
problem, then you must need PhysOpt!".
I just love it!
- [ BeetleJuice ]
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