( ESNUG 349 Item 6 ) --------------------------------------------- [4/18/00]
Subject: Testing The Waters; RTL Signoff Still Needs Gate Level Simulation
> "People are missing the point here. We need levels of abstraction to
> be removed -- not added! In the not too distant future we'll need
> RTL-level sign-off and we'll also need good RTL-level power, area, and
> timing estimation tools."
>
> - Steve Golson of Trilobyte Design
>
> "We already do RTL sign-off today. It doesn't make sense that every
> designer knows synthesis details. We just have one engineer in our
> group that does that and the rest of us write the Verilog RTL."
>
> - Paul Zimmer of Cisco Systems
From: Frank Emnett <frank@aiec.com>
John,
In talking with other designers at the SNUG conference and elsewhere, it
seems like many folks run what is almost an RTL signoff flow in house, but
they all seem to run some level of gate-level simulation for a sanity check.
Something I haven't really seen discussed (would make a great SNUG paper
for someone with this knowledge) is why do we still need to run gate-level
simulations? What problems do they uncover?
Personally, I've caught the situation recently discussed in ESNUG where
uninitialized registers driving if-then-else statements simulate one way
in RTL simulation, as if the registers were actually initialized to some
good value, and in gate-level unknowns propagate all over the place. I've
also seen situations where assumptions were made regarding scan insertion
and ATPG that aren't necessarily true (set_scan_transparent,
set_test_assume), so some set of ATPG vectors need to be run at the gate
level. Equvalence checking won't help with these issues. Are there others?
I think that the issue is not so much the time needed for gate level
simulation, since usually a very limited subset of the full regression suite
is run at gate level, but rather is the late point at the design cycle in
which problems are uncovered by gate level simulation causing some sort of
scramble to fix them at the last minute.
Do you folks try to run gate-level sims on some non-optimized quickie
synthesized netlist earlier in the flow? Or is there any way to completely
eliminate the need for these gate level sims, through adherence to certain
design practices? Are there any RTL analyzers that can help with this?
- Frank Emnett
Automotive IEC Phoenix, AZ
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