( ESNUG 348 Item 12 ) -------------------------------------------- [3/30/00]
Subject: ( ESNUG 346 #13 ) DC & PrimeTime Can't Read The SDF They Write
> We are modeling flop output-to-output timing arcs in our .lib. That is,
> we have CLK->QB and QB->Q arcs. DC handles these just fine until it
> comes time to write an SDF. Then it decides to simply write CLK->QB and
> CLK->Q arcs. The delay numbers are correct, but of course this file
> cannot be imported into DC because of arc mismatches!
>
> SolvNET revealed that each tool may or may not have its own SDF writer
> code. (See Static_Timing-171.html and Static_Timing-191.html). In my
> opinion their proposed workarounds are laughable.
>
> Has anyone been through this before and found which tool's SDF writer
> produces the most 'reasonable' (i.e., bug-free, actually USABLE) output?
>
> - Andy Pagones
> Motorola Labs
From: Tom David <tomd@silogix.com>
Hi John,
I've run into a similar problem using the Synopsys SDF writers and readers
out of DC and PrimeTime. I've basically given up using the SDF writers in
DC/PT and mostly use Ultima/MDC. They seem to generate the most reasonable
SDF that back annotate both to the .lib file and to my Verilog/VHDL models.
The timing checks sections for these standard cell models (for both VITAL
and Verilog) are generated directly from the .lib via a Perl script that I
wrote.
- Tom David
Silogix
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