( ESNUG 348 Item 5 ) --------------------------------------------- [3/30/00]
From: John Russo <jfrusso@lucent.com>
Subject: The Odd `resetall & `uselib Differences Between VCS & Verilog-XL
Hi, John,
It appears that with VCS a `resetall compiler directive causes the search
path for levels below the current hierarchy to be a empty set. This applies
to all files except those in the current file. Verilog-XL does not change
search enviornment as a result of `resetall.
Verilog-XL and VCS behave differently in another way. I've found that with
Verilog-XL when a uselib directive is used in a model that instantiates
parts, all searches at that level will honor that uselib statement. In
other words, if a module instantiates parts and uses a `uselib statement to
control the search path, then all searches at that level will use that
search path until another uselib statement is encountered. For example,
suppose I had a module in a `uselib enviornment of liba (`uselib dir=liba
libext=.v) and suppose I instantiate two parts: a1 and b1. If I put a
`uselib statement inside the code for a1 to control the search for sub-part
a11, then all parts at the second hierarchical level would use the second
enviornment. In other words part b11 which is instantiated by part b1
which is in the top level search enviornment will ONLY be searched in the
second level enviornment that the uselib statement in a1 specified.
Interestingly enough VCS5.1 behaves identically, but VCS5.0 maintains the
top level environment for the second part.
- John Russo
Lucent Technologies Allentown, PA
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