( ESNUG 344 Item 12 ) -------------------------------------------- [2/23/00]
From: Robert Wood <rwood@spacebridge.com>
Subject: 2-D VHDL Arrays Don't Make It When DC 99.10 Writes Out Verilog
One of our designers has reported a problem with version 99.10 of Design
Compiler. The problem occurs when writing out Verilog from VHDL source.
It occours on 2 dimensional array signals, I believe. Has anyone else met
this problem. Somehow, given as it's a wierd construct to start with,
I'm a) not surprised, and b) all alone?
- Robert Wood
Spacebridge Networks
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