( ESNUG 344 Item 10 ) -------------------------------------------- [2/23/00]
From: [ Norman de Plume ]
Subject: Synopsys Doesn't Support SDF COND (Even Though They Claim They Do)
Hi John, (please keep me anon)
I'm developing a Synopsys .lib model for a complex RAM cell that doesn't
have all the traditional built-in latch functions. Because of this, the
.lib has several SDF COND branches, which I haven't been able to simulate
properly. I don't know if many of your other readers use SDF COND branches,
John, but DC 99.10 was the first release to support SDF COND TIMINGCHECKs
(sort of). This is from Synopsys:
This is regarding "conditional timing checks can not be read into
simulation tool (Verilog XL)".
I have duplicated your problem, and I have filed a bug report on your
behalf. The bug report number is STAR xxxxx. You are absolutely
correct. The conditional timing checks written out by the tool does
not follow the SDF v2.1 specification.
The workaround is to modify the resulted SDF manually or use PrimeTime
to generate the file.
Just thought I'd pass this along to your readers.
- [ Norman de Plume ]
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