( ESNUG 343 Item 5 ) --------------------------------------------- [2/16/00]
From: Michael Jarchi <jarchi@vitesse.com>
Subject: DC 99.05/.10 Isn't Carrying "Don't Care" X's Correctly In Casex
Hi John,
Here's a recent issue I found with Synopsys DC 99.05/.10 that other users
may be interested in hearing about. I have a wire defined as:
assign mask3 = {byte1[7],6'hx,byte1[7],byte2[7],byte2[7],5'hx,byte2[7],
byte1[6],6'hx,byte1[6],byte2[6],byte2[6],5'hx,byte2[6],
byte1[5],6'hx,byte1[5],byte2[5],byte2[5],5'hx,byte2[5],
byte1[4],6'hx,byte1[4],byte2[4],byte2[4],5'hx,byte2[4],
byte1[3],6'hx,byte1[3],byte2[3],byte2[3],5'hx,byte2[3],
byte1[2],6'hx,byte1[2],byte2[2],byte2[2],5'hx,byte2[2],
byte1[1],6'hx,byte1[1],byte2[1],byte2[1],5'hx,byte2[1],
byte1[0],6'hx,byte1[0],byte2[0],byte2[0],5'hx,byte2[0]};
And used in the RTL as:
casex({ena1, ena2, ena3, ena4, DATA[191:0]})
{1'b1, 1'bx, 1'b0, 1'b1, 1'bx,mask1,63'hx}: flag <= #1 1;
{1'b0, 1'b1, 1'b0, 1'b1, 1'bx,mask2,63'hx}: flag <= #1 1;
{1'b0, 1'b0, 1'b0, 1'b1, 1'bx,mask3,63'hx}: flag <= #1 1;
default: flag <= #1 0;
endcase
Well, it turns out DC is not carrying the "don't care" x's over into the
casex statements correctly when analyzing/mapping/etc of the RTL.
Verilog-XL sims are functionally correct, but the gate-level are wrong.
When I edit the RTL and place the wire assignment value directly into the
casex statements, all is fine with the Synopsys gate-level result. I let
Synopsys know about this problem and they have been examining the problem
for the last several weeks. If it is an illegal coding style, Synopsys DC
never complains about it.
- Mike Jarchi
Vitesse Semiconductor Corp. Camarillo, CA
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