( ESNUG 342 Item 13 ) -------------------------------------------- [2/03/00]

From: [ One Of The 47 Ronin ]
Subject: How Should A Foundry Craft A .lib That's Optimal For Synthesis?

Hi John,

I always enjoy ESNUG POST, and I often find good information in there.  This
is the first time I send E-mail to you.  Please keep me ANONYMOUS.

We acknowledge if we change Synopsys .lib slightly on its cell repertoire or
cell timing value, the sythesis result is affected much.  When we added some
new cells, the synthesis result became worse in some cases.  We changed the
cell timing a little bit faster, the result was much improved.

We know that constraints, WLM, cell area and many other factors are related
to determine the synthesis result.  But we would like to know if someone has
a guide line of developing the library: how we should develop library
optimal for Design Compiler.  We tried to find out any application note
and/or documents on Synopsys SolvNET Web and contacted our Synopsys AE, but
we can not get useful information so far.

If someone give us such information on ESNUG, it's very appreciated.

    - [ One Of The 47 Ronin ]



 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)