( ESNUG 342 Item 6 ) --------------------------------------------- [2/03/00]
Subject: ( ESNUG 341 #7 ) Users Critique Altera Quartus & FPGA Compiler II
> As part of the verification of our ASIC design, we plan to build an FPGA
> based prototype using Altera 20K Apex devices. Unfortunately we're having
> problems compiling our VHDL directly w/ Quartus (Altera's Apex software).
> We get lots of 'internal' errors, plus it appears that Quartus is quite
> restricted in its VHDL support. Another option would be to use Synopsys
> FPGA Compiler II. I was wondering if anyone has had any stories about
> using FPGA Compiler II in conjunction with Altera Quartus ?
>
> - Justin Smith
> Atmosphere Networks Osborne Park, Western Australia
From: [ The Cat In The Hat ]
John, keep me anon.
My company works in VHDL targeted to both ASICs and FPGAs. Our experience
is that if you want good quality results and few language hassles, you have
to use either Exemplar or Synplicity.
- [ The Cat In The Hat ]
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From: Jay Dowling <jay@acut.com>
If you want the smallest, fastest results and want to get them in the least
amount of time when synthesizing Verilog, VHDL, or a combination of both to
any FPGA architecture, then you should be using Synplify. They support
both languages better than anybody else.
- Jay Dowling
Acut
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From: Brian Carlton <carltb@ntd.comsat.com>
John,
I think the problem is in the Altera place and route part. I am using
Synplicity for synthesis, and I still have plenty of the sorts of problems
Justin describes.
- Brian Carlton
Comsat
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From: Gaedke Klaus <GaedkeK@thmulti.com>
Hello, John,
We have just finished a 30k design using FPGA Compiler II (Altera Edition).
We were able to set up a stable design flow within a few days. FPGA
Compiler II accepts VHDL RTL-code exactly like Design Compiler, therefore
we did not get any error messages for a design previously synthesized by
Design Compiler. The tool is stable and has a stable link to Quartus
(either flat or hierarchical EDIF). The run time is OK (about 1 hour for
30k gates on an Ultra Sparc 60). LPMs are supported. Post-synthesis
verification of the netlist did not show errors. One thing you can't trust
are the timing estimations, we found a difference of factor 6 (!) between
FPGA compiler II prediction and Quartus timing report. Besides that: it's
good stuff!
- Gaedke Klaus
Thmulti
---- ---- ---- ---- ---- ---- ----
From: Kathy Brown <kbrown@ti.com>
Hi, John,
I'm happy to have something to contribute to the discussion, as I have often
profited from ESNUG myself.
We've been using FPGA Compiler II on our project for about 2 months. (Ver
3.3.0.4517, we stopped using version 3.3.1.4719 when Quartus could not read
the EDIF files it created). We were urged to use FC2 for synthesis, rather
than synthesizing with Altera Quartus, tool by Altera themselves. The
reason was that they felt we would get better timing closure as the tool
comes from a place where synthesis is their bread and butter.
Initially we found that we got smaller area results from FC2, and good
timing. We have not gone back to make any more comparisons.
DC-shell users will find the GUI somewhat painful, with very few options.
I tried to figure out fc2_shell, the equivalent command line version of the
GUI but could not get adequate documentation. Synopsys support said there
was no reference guide for fc2_shell but they had some informal notes which
they sent. The commands were very basic -- not what I was looking for
(set_dont_touch). Due to time pressures, I continued to use the GUI
instead. If your design is less than 70% full and doesn't push timing too
much, then this is a decent option.
However, if you are trying to squeeze your design in (93% of capacity) and
still meet timing, good luck. Our solution was to reduce the logic to less
than 70% of capacity and wait for the larger parts (600E in March '00).
The tool gives two basic options: optimize for area or speed, and each with
a level of effort (low, high). My experience with optimizing for speed was
that it tended to eat up the whole device, even with a design which was 65%
full if optimized for area. Not too spiffy for practical reasons. My
experience with optimizing for area did not show any such problems, and the
speed was very similar to the one which was optimized for speed (the speed
comparison was done after place and route with Quartus, see below).
About the speed numbers from FC2 -- totally unrealistic. Whatever they are
using for the equivalent of a wire load model is woefully inadequate.
Numbers like 100 MHz before P&R become 14 MHz after P&R! (I did not get as
good timing numbers from a Quartus compile followed by a Quartus P&R, to be
honest though.)
Another issue I came up against is that FC2, at this time 99.10 version,
does not support the use of the memory blocks as logic blocks. For a
design which is pretty full to capacity and not using much memory, this is
a great option. Synplicity is able to do this, and possibly other tools,
I'm told. I also heard that this capability may be in the next version of
FC2. The local support is looking into a work-around within FC2, but I
haven't heard back from them in a week.
All in all, I would recommend FC2.
- Kathy Brown
Texas Instruments Dallas, Texas
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