( ESNUG 341 Item 14 ) -------------------------------------------- [1/26/00]
From: Gzim Derti <gderti@intrinsix.com>
Subject: DC 99.05-4 "set_wire_load -selection_group" Attribute Won't Set!
Hi, John,
A few observations that I've been making lately concerning Design Compiler
99.05-4 (I know, I'm behind a rev, but this might carry forward...)
I'm currently working with a vendor's library that contains wire_load_models
for both 4 and 5 Layer Metal. I've got to try and force DC to use the
4LM only. So, I read the manual and it talks about a -selection_group
switch which should do this for me. I try and do the following...
set_wire_load -mode enclosed -min_block_size 20000 -selection_group 4LM
do a report_attribute on the design, and guess what, the selection_goup
attribute is unset! On a whim, I try and do a "compile -no_map" followed
by the same command as shown above, and low-and-behold, the attribute can
NOW be set on the design in question. So, now my sequence of events for
a working compile is...
apply constraints
compile -no_map
apply constraints AGAIN
compile -map_effort.........
(grumble, grumble, grumble........)
On a side note, I've noticed that DC is MUCH better at choosing the faster
DesignWare parts if you perform a "compile -no_map" BEFORE you do a
"compile -map_effort". Don't ask me why, but that's what I'm seeing lately.
Anyway, basically I'm just venting and hoping to help someone else through
this ever deepening quagmire known as Design Compiler.......
- Gzim Derti
Intrinsix Rochester, NY
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