( ESNUG 341 Item 12 ) -------------------------------------------- [1/26/00]
Subject: ( ESNUG 338 #6 339 #4 ) DC/PT 3-D Load-Dependent Lookup Tables
> I am wondering how this can be true: "Setup/Hold depends on loads on both
> Q and Qbar." from the SYNOPSYS CAE' statment. For DFF's, we see a
> master/slave architecture. Otherwise, it is a LATCH. So, the setup time
> of a DFF should not be affected by LOADING, since the loading is blocked
> and afftected only the slave stage. What I am missing here??
>
> - [ Made In Taiwan ]
From: [ The Synopsys Library Compiler CAE ]
Hi John,
This is in response regarding the ESNUG 339 #4 3-D lib queries.
On my earlier response regarding 3-D constraint tables: Setup/Hold
constraints do not depend on loads on Q and Qbar. In fact the 3-D constraint
tables are indexed by the related pin, the constraint pin and the load on
the related output pin.
> The Synopsys .lib has become a very popular format which can be parsed by
> many tools (from Synopsys and other vendors). Along with this development
> additional commands and constructs like the 3-D tables were added. These
> are very well described in the Library Compiler Manuals, what is missing
> is a list or table of tools that can read this information and actually
> use it in a meaningful way. Let me give an example.
>
> /* Library defaults */
> slew_lower_threshold_pct_rise : 20.00 ;
> slew_upper_threshold_pct_rise : 80.00 ;
> slew_derate_from_library : 1.00 ;
> input_threshold_pct_fall : 50.00 ;
> output_threshold_pct_fall : 50.00 ;
> input_threshold_pct_rise : 50.00 ;
> output_threshold_pct_rise : 50.00 ;
> slew_lower_threshold_pct_fall : 20.00 ;
> slew_upper_threshold_pct_fall : 80.00 ;
>
> The above lines are only meaningful to PrimeTime. There is no hint to
> this in any documentation that I looked at, so a user may have the
> impression that all Synopsys tool understand this.
>
> - Stefan Scharfenberg
> Motorola SoCDT Munich, Germany
Regarding Stefan's enquiry about how the tools use different attributes
in the library, Chapter 4 ( Technology Library Attributes ) of the Library
Compiler Reference Manual Vol 1, has a list of all the attributes, the
different levels ( library, cell, pin ) where they are used in the library
and the different tools that use them ( like synthesis, test, fpga ). We
do not explicitly have tool names like DC because liberty is now an open
format and there are lots of other EDA vendor tools that use these
attributes. This table has been very useful for all the people that use
Liberty.
> Synopsys version 1999.10 supports 3-dimensional lookup tables for delay
> modeling. I hope to find out what other tools (e.g., Avanti, Cadence,
> etc.) already have or plan to have compatible timing modeling. What have
> you heard from your vendors? Are there characterization tools out there
> that can write .lib's with this syntax?
>
> - Andy Pagones
> Motorola Labs
Regarding Andy's question on 3-D delay tables, usually ASIC vendors have
their own characterization tools and there are a couple of ASIC vendors
who write out characterized data in this format. Lots of other EDA vendors
support the Liberty Tap-In program and I am not sure which tools exactly
support this particular feature, but a lot of tools from different EDA
vendors read timing information from Liberty.
- [ The Synopsys Library Compiler CAE ]
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