( ESNUG 341 Item 11 ) -------------------------------------------- [1/26/00]
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Subject: Strange Timing Bug Found In Synopsys VHDL VSS 99.10 Simulator
Dear John,
I want to share with you and the ESNUG crowd an amazing VSS bug. I had
this fragment of code:
p0 : process (clk, GSR)
begin
if (GSR = '1') then
addr_d <= (others => '0');
elsif (clk'event and clk = '1') then
addr_p <= ui_addr;
end if;
end process;
that refused to simulate the way it should with VSS 99.10. addr_p was not
the registered version of ui_addr, but an identical copy of it. After a
few hours I discovered that the problem was with the "addr_p" identifier:
changing the name of the signal to "addr_d" solved the problem. Isn't this
amazing?
- Dr. Arrigo Benedetti
Caltech Pasadena, CA
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