( ESNUG 341 Item 8 ) --------------------------------------------- [1/26/00]
Subject: ( ESNUG 340 #8 ) I Disagree With Zain's Use Of "Initial" Blocks
> The three categories of a synthesis subset are "Supported", "Not
> Supported", and "Ignored". Synthesis tools ignore initial blocks, and
> it is not wrong to use these statements in synthesizable code. Note that
> these examples are not presented as synthesizable descriptions. Initial
> blocks are useful for pre-synthesis simulation of state machines that do
> not have any hardware resetting mechanisms. This section presents a
> basic state machine and adds to it in the later sections. Without a
> resetting mechanism, the only way to simulate is to use an initial block.
> With resetting mechanism, it is still a good practice to use initial
> blocks. Page 252 shows a state machine with an asynchronous reset.
>
> - Zain Navabi
> Author of "Verilog Digital System Design"
> Northeastern University Boston, MA
From: Vigyan Singhal <vigyan@home.com>
Dear John,
I must disagree strongly with one comment in Prof. Navabi's response to his
book review by Cliff Cummings.
The use of initial blocks for synthesizable blocks is extremely dangerous.
First, if the state machines do not have any hardware resetting mechanisms,
that is clearly not a synthesizable state design. Even otherwise, let's say
you use an initial block to initialize a design for RTL simulation. This
makes the sematics of RTL and synthesized gate-level different, and is very
dangerous. Consider a flow where you simulate only the RTL and use formal
equivalence checking to verify the equivalence of RTL vs gate-level. The
following may very easily happen:
RTL simulates fine. Synthesis has no bugs, and formal equivalence checking
approves the equivalence of RTL vs gate. However, the real gate-level
does not initialize correctly because synthesis (and equivalence checking)
ignored the initial blocks. But since you didn't do any gate-level
simulation, you're dead!
On the other hand, if you do not rely on initial blocks, this cannot happen.
Anytime your RTL has different simulation and synthesis sematics, you are
opening up a dangerous gap in the otherwise reliable static verification
flow. As Cliff orginally said, the use of initial blocks should be
restricted to testbenches in an ASIC design design flow.
- Vigyan Singhal
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