( ESNUG 341 Item 5 ) --------------------------------------------- [1/26/00]

Subject: ( ESNUG 340 #3 )  Make "Fake" DC Library Elements With Sub-Designs

> Is there a way to create a Synopsys library element from a design so that
> Synopsys treats the subdesign as a library component?  Say, for instance,
> I have a large design that is made up of many subdesigns; I'd like to be
> able to replace one or more of the designs with a Synopsys library
> component to cut down on the memory usage to make things run faster, etc.
> (And for the moment, lets not worry about loading ...)
>
>     - Tom Cruz
>       IBM Microelectronics Division


From: Brian Kane <briank@torrentnet.com>

Hi John,

Have him look at the DC "model" command - I think it does what he wants.

    - Brian Kane
      Ericsson IP                                  Silver Spring, MD

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From: [ A Synopsys PrimeTime CAE ]

John,

It sounds like PrimeTime's model extraction will do exactly what Tom wants.
You load in a netlist, extract the model of any arbitrary subdesign, and
presto - PrimeTime gives you a single-cell linkable .db file which contains
a macrocell with all the proper timing and load/drive behaviors.  You can
plop one or more of these down in DC or PT or Chip Architect or whatever,
and have it faithfully act like the design (without having all the baggage
of those gates in memory).

    - [ A Synopsys PrimeTime CAE ]

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From: Scott Evans <scott@sonicsinc.com>

Hi, John,

Would a STAMP model serve his needs or is that more than you were looking
for?  You would need access to PrimeTime.  The essential commands you need
are extract_model and compile_stamp_model (as well as being sure to set
the various extract_model* variables).

    - Scott Evans
      Sonics Inc.                           Mountain View, CA

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From: [ Another Synopsys PrimeTime CAE ]

Hi John,

It sounds like a perfect use for model extraction, but since he has
searched the manuals I assume he's looked at the PrimeTime Modeling User
Guide, and I could be missing something instead.

Model extraction allows you to create a timing model (essentially, a
somewhat complex library element) from any gate-level netlist.  Its purpose
is as you say to cut down on memory usage and CPU analysis time.  You can
replace n blocks in your design with extracted models.  These models capture
the worst-case/best-case paths from primary inputs and leading to primary
outputs.  Internal register-to-register paths are discarded as they are
generally not needed in the full-chip context (they can be analyzed at the
block-level).  You have the choice of generating a .db version of the model
(PT and DC think of it as a compiled .lib) or a Stamp source file, but
not .lib.

You basically set up the design you want the library element for, create the
clocks, false paths, MCPs, etc., then tell PT to create the element for a
particular operating condition:

  extract_model -library_cell -output mymodel -operating_conditions {WCCOM}

Not all library cell attributes are preserved in the model (but area is
preserved.)

    - [ Another Synopsys PrimeTime CAE ]

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From: Oren Rubinstein <oren@gigapixel.com>

John,

Design Compiler has a command called "model", which does everything you
need, including updating the library.  After Tom models his design, he
should use remove_design to get rid of the original.

    - Oren Rubinstein
      GigaPixel Corp.                            Santa Clara, CA