( ESNUG 340 Item 6 ) --------------------------------------------- [1/19/00]
Subject: ( ESNUG 335 #9 338 #3 ) Janick Critiques Co-Design's Superlog
> So far we are getting positive feedback from the people we talk to, but
> are always interested in other opinions. Here is a chunk of Superlog
> code to provide a feel of how it looks: ...
>
> function ref node treeFind(string str, ref node parent);
> if (parent == null) return null;
> visited++;
> if (str == parent->s) return parent; // string compare
> if (str < parent->s) return treeFind(str, parent->left);
> else return treeFind(str, parent->right); // recursion
> endfunction
> ...
> Do you have any feedback on the approach we are taking? Do you think your
> readers are interested in this approach?
>
> - Dave Kelf
> Co-Design Automation, Inc. Melrose, MA
From: "Janick Bergeron" <janick@qualis.com>
John,
The Superlog state machine description in ESNUG 338 #3 looks a lot like the
FML2 description used in Nortel's early in-house synthesis tool, back in
1989. I'm sure other languages designed for synthesis have similar
features. Cool.
> state {S0, S1, S2} cstate; // state variable with enumeration
Can these enumerals be used in any expressions (like VHDL's) such as
"if (cstate == S0) ...", or is it limited to transition statements (I'd
prefer the former)? Can they be overloaded?
> always @(posedge reset)
> transition (cstate) default: ->> S0; endtransition
> ...
> always @(posedge clk iff !reset)
> transition (cstate)
> S0:if (inp == 0) ->>S2; // change state
> S2:if (inp == 1) ->> S1; else ->> S0;
> S1: ->> S0 n = treeFind("shergar", root);
> endtransition
I object to this style! Why did you have to use two parallel constructs for
two operations that are clearly mutually exclusive? Sequential code is
perfectly acceptable and should be preferred to parallel code. What if
those two blocks were separated by several other "always" and "initial"
blocks? It would be difficult to figure out the functionality of the
state machine.
If you're creating a state machine statement, why not go all-out? e.g.:
fsm
async (reset == 1'b1): -->> S0;
transition @ (posedge clk): cstate
...
endtransition
endfsm
Also, what is the user forgets your "iff !reset"? Do you get a race
condition? What if the reset is generated using a block like this:
begin
...
@ (posedge clk);
rst = 1'b1;
....
end
Is it possible for the "posedge clk iff !reset" to be interpreted
differently because of the execution order?
> S1: ->> S0 n = treeFind("shergar", root);
^
Aren't you missing a semi-colon here? Or is it a compound statement like
the @, # and wait statements in Verilog? (which I would object to;
sequentiality should be described using separate statements).
> function ref node treeFind(string str, ref node parent);
Hurray! High-level data types on Verilog interfaces! I hope you do proper
type checking in expressions and interfaces as in ANSI-C, not K&R C....
Are Superlog tasks re-entrant, too?
I was going to ask for functions and tasks inside structs with inheritance,
virtual subprograms, etc... but then I'd be asking Superlog to become a
mix of e and VERA. :-)
- Janick Bergeron
Qualis Design Corporation Somewhere, Oregon
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