( ESNUG 340 Item 3 ) --------------------------------------------- [1/19/00]

From: Tom Cruz <tomcruz@us.ibm.com>
Subject: How Do You Create "Fake" DC Library Elements From Sub-Designs?

Hi John

Is there a way to create a Synopsys library element from a design so that
Synopsys treats the subdesign as a library component?

Say, for instance, I have a large design that is made up of many subdesigns;
I'd like to be able to replace one or more of the designs with a Synopsys
library component to cut down on the memory usage to make things run faster,
etc.  (And for the moment, lets not worry about loading ...)

We have done this in the past by creating a script to parse VHDL, add some
technology header stuff, and create a .lib file.  Then we just do a read_lib
and write_lib of that file and we're done.  The problem with this method is
when designs use different types or records in the port statements instead
of std_logic or std_logic_vector.  Then we're stuck looking through files
for the type declarations to do some manual cleanup.  And of course, if a
port changes, you get to do it all over again.

At a minimum, we'd be happy with a component that has the proper port map
and links properly, but of course a more ideal solution would be to have
the library component reflect the area number and loading of what it
represents -- almost like a technology library book.

It seems like Synopsys should have some way of doing this automatically,
but I've looked through the manuals and so far I haven't seen anything
to do this.  Any ideas?

    - Tom Cruz
      IBM Microelectronics Division