( ESNUG 337 Item 4 ) -------------------------------------------- [11/18/99]
From: "Sean Atsatt" <seana@sierraimaging.com>
Subject: Better Multipliers Without Having To Buy A Pricey DesignWare Lib
Howdy John,
Some info that might be of interest to your readers.
We recently lost access to the multiplier macro's that we have been using.
We tried the basic Synopsys DesignWare multiplier, but it couldn't meet our
requirements. We took a look at buying the DesignWare library, but a year
license was absurdly expensive just to get a multiplier. We were going to
do our own Wallace tree multiplier, but I thought maybe I should check the
web first. A quick search turned up a site that automatically builds custom
VHDL or Verilog code based on your arithmetic requirements. We tried it,
downloaded, synthesized and simulated the generated code. Works great! It
took about an hour to go through the whole process. (Synopsys scripts are
provided). We obtained performance and area similar to custom macro's we
had been using. They have an automated verification tool that will verify
your function in an FPGA, but this didn't work for us. We are running an
exhaustive check on the macro's we generated. (This will take a couple of
days of CPU time, but we have that).
The project is at: http://modgen.fysel.ntnu.no/~pihl/iwlas98/
The tool is at: http://modgen.fysel.ntnu.no
If any of your other readers have experience with this tool it would be
interesting to hear about.
- Sean Atsatt
Sierra Imaging, Inc.
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