( ESNUG 334 Item 8 ) --------------------------------------------- [10/28/99]
Subject: Five Chip Designers Discuss The Foolishness Of C-Based HW Design
> "I agree with Geir," John Reynolds of Intel quickly replied, "Evaluate
> some of the tools and you will quickly see how restricted you are and the
> things you cannot model. The observation that one engineer had around
> here when discussing the C/C++ vs. HDL argument was that the more you
> restrict C++ by using class templates, etc., the more you shave the
> language so that you can synthesize it, the more funky crap you add into
> the language to simulate concurrency already found in HDLs, the more your
> 'language' approaches a Verilog or VHDL!"
>
> - from "Back To The C++ Future"
From: John Reynolds <jreynold@sedona.ch.intel.com>
Hey John ...
You're making me famous around here ... my "C++ as an HDL language sucks"
editorial that's now in EE Times is the talk of the water cooler here ... :)
I still think it's a dumb idea... I was in a conference call yesterday with
the folks from Synopsys talking about this "SystemC" stuff. Some parts I
like, but others are just too much trouble -- you'd might as well just learn
VHDL or Verilog (so my theory is confirmed, once again :).
I just wish somebody would take VHDL and Verilog and merge them in the
middle. VHDL is "too high level". But I'd miss some constructs from VHDL
in Verilog and thus it seems "a little less high level than it should be."
- John Reynolds
Intel
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From: "Anders Nordstrom" <andersn@nortelnetworks.com>
John,
Check out what the guys at Co-Design http://www.co-design.com are doing.
They are creating a new language, Superlog, which is essentially an
evolution of Verilog combined with C. The best thing is that it will still
work with either today's Verilog or C so you don't have to start from
scratch with a new language.
Also keep an eye out for the new Verilog standard, Verilog-2000. It is not
C++ but it addresses many of the problems designers have today.
- Anders Nordstrom
Nortel Networks Ottawa, Ontario, Canada
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From: "Robert McLellan" <robm@nortelnetworks.com>
Dear John,
Loved your comments about C/C++, internal CAD at large system companies
having already "been there done that", etc. If there's anything that's a
hallmark of the EDA business, it's that in general it's a marketplace that
suffers from a high degree of "amnesia". It also begs the question of why
we persist in looking for the "grand unification theory" approach to all of
this... has anyone clearly identified the "problem" that matches their
simple "solution"?
As a friend once said, people don't want simple answers, they want simple
questions!
Good stuff... keep it up.
- Rob McLellan
Nortel Networks Nepean, Ontario, Canada
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From: "Gary Greenstein" <greenstein@asic-alliance.com>
John,
Seems to me that there's one big difference: with C/C++ designs, you get
(more or less) free simulation. You just need an underlying event
management library, be it from an industry-wide effort or your own. Just
compile the program, and you have a simulation environment. It also allows
for very fast API access.
- Gary Greenstein
ASIC Alliance Corporation
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From: "Kanu Emeruwa" <kemeruwa@newbridge.com>
John,
Is there no merit in a push for one standard language for ASIC development?
At Newbridge we currently use VHDL, e (Specman), C/C++ and we can't get away
from Verilog (RAM models, netlists) not to mention scripting languages Tcl,
Perl, csh.
Tcl appears to be gaining some ground with the EDA companies, how about an
HDL? Let's pick just one whether it's back to the future or not. I won't
hold my breath waiting though. Your article probably rightly has the effect
of braking the current excitement.
- Kanu Emeruwa
Newbridge Networks Corp.
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