( ESNUG 334 Item 3 ) --------------------------------------------- [10/28/99]
Subject: ( ESNUG 329 #11 330 #3 ) Converting Transistors Into Schematics
> If this user wants extract the functionality of the cell and generate a
> truth table, there are two ways to look at the problem:
>
> 1) lots of library characterization tool vendors perform this step
> automatically as part of the delay measurement process
>
> 2) it is very difficult because of issues with dynamic logic,
> pass-gate logic, and feedback cells (i.e. flip-flops)
>
> These aren't contradictory; the tools tend to fall down when given "messy"
> cells. He may need to hire some outside help to do this tranlation by
> hand or, of course, the library characterization vendors would be only
> too happy to help you -- for a price.
>
> - David Chapman
> Chapman Consulting Santa Clara, CA
From: Christian.Jay@infineon.com ( Christian Jay )
Hi, John,
We are currently here in Siemens/Infineon in evaluation process with a new
small company located in the South of France. They have a beta-version of
TraLaLa (Transistor Level Analysis and Logic Abstraction) which proposes
unique features such as automatic recognition of dynamic logic, pass logic,
sequential logic structure recognition, structural pattern matching of
identical structures, ...
More info can be found at : <http://www.sansistor.com>
- Christian Jay
Infineon Technologies / Siemens Sophia Antipolis, France
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