( ESNUG 333 Item 1 ) --------------------------------------------- [10/20/99]
Subject: ( ESNUG 331 #6 ) Start-Up Verplex Tramples Chrysalis & Formality
> I saw this posting on ESNUG about problems with Chrysalis. Have you
> looked at Verplex? <http://www.verplex.com> Using it, we've found it
> runs at least 10x faster and handles greater than 300K gate comparisons.
> The key to getting equivalency checks working are:
>
> 1. pre-mapping all gate-vs-RTL state points (flip-flops) before
> comparison
> 2. matching RTL hierarchy with gate hierarchy
> 3. correctly modelling your flip-flops (gate often sees them as two
> latches)
>
> We've eliminated gate-simulation with Verplex. Good luck with your
> million gate designs and please keep me anonymous.
>
> - [ To Have And Have Not ]
From: [ Big Brother Is Watching ]
Hi, John,
Anonymous, please, big brother is watching.
In regards to the discussion going on regarding equivalency checking, I have
some direct inputs. I have been evaluating EC tools for 4-5 years for 2
different companies.
I started out looking at Chrysalis on 50-60k gate ASICs and immediately
found a synopsys introduced logic bug. That really turned me on (especially
since gate level verification usually fell in my lap). I always hated the
fact that Chrysalis choked on blocks greater than about 10k for RTL2GATE
compares. It has always seemed that they are behind the current block
synthesis curves during each subsequent release of their tool. I also
thought that their UI was "lame". It had too many options, holes, and
commands for a tool that was supposed to save so much time. Also, I found
that when I wrote a script to do say RTL2GATEs on 1 block, it was useless
for another block or for GATE2GATE runs on the same block.
I then looked at Formality. It seemed to have a pretty nice frontend (but I
hate GUIs... give me an xterm and emacs and I can design the world). The
local support center basically had no expertise on the tool or even EC
techniques for that matter, so they were of no help. I also had a block
that I wanted to do RTL2GATEs on to compare to Chrysalis. The block was in
the 300k range but the gates were flattened. Chrysalis bombed. Formality
bombed. I gave the RTL to the local support center and after 7 months still
no word.
I thought to myself that it must be an impossible task. I would have to
break the problem up. So I fast synthesized the RTL with hierarchy, ran a
hierarchical EC with Chrysalis, and then ran a GATE2GATE with Chrysalis
(A=B; B=C; so A=C) and got that to finish (with the exception of 1 block)
after alot of work. (note this is a 300k block out of a 6.5M ASIC). My
sweet dreams of easy verification of this chip suddenly turned to
nightmares ...
Then, I was introduced to Verplex. Within 2 hours of getting the tool
installed (and no design center support), I had an RTL to Flat Gates
comparison completed on the 300k block. Of over 6k key points in the block,
I had almost all equivalent with the exception of 16 aborted points. I then
talked to the AEs for Verplex, and had a new release in no time that took
care of the abort points (interesting to note that the aborted points were
logic cones in the module that chrysalis could never do!). All of this with
only 10-15 lines of scripting (definitely not like the Chrysalis tool!). I
then tried the same block targeted to another vendor...BANG! a synopsys bug
found with critical state points dropped. I have found that Verplex does a
great job on RTL2FLATGATES and RTL2HIERGATES on blocks <350k. Either 10x
performance over the competitors or it completes and they don't. Also, the
memory usage seems to be about 1/2 to 2/3 of the competitors. For post
layout/test-insertion/ECO, I can do my 6.5M gate design in less than 1.5
hours.
I also hacked dc_perl (you remember this don't you) to form lec_perl. It is
beautiful for parsing and analyzing a design in Verplex. I can take a block
with test inserted, find the key control signals and force them to
functional mode with 1 command now rather than searching for them. It
really helps when I don't know squat about the block I am verifying. As for
the flop->Master/Slave issue, Verplex can identify and fold the MS latches
back into flops (no cruddy library prep step like Chrysalis). My vendor's
SEs (a large.. did I say copper interconnect.. ASIC vendor) couldn't believe
the results I was getting for GATE2GATE versus their runs with Chrysalis.
Their runs take 24 hours, mine takes 1.5 hours.
On the downside, their tool is new, so there are a few "issues" once in a
while. But, for the results I am getting, I don't mind helping them debug
and enhance their tool! They are suprisingly fast at turnaround time to for
new releases to fix issues. (Guess that's a small hungry company for you.)
- [ Big Brother Is Watching ]
[ Editor's Note: As with *ALL* anon letters that give strong opinions, I do
background checks to ensure they are legitimate. I know who wrote this.
He's a chip designer. He's posted here before. It's legit. - John ]
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