( ESNUG 330 Item 6 ) --------------------------------------------- [9/30/99]
Subject: ( ESNUG 329 #21 ) One Customer Reviews The Revamped DW PCI Core
> Has anyone successfully use the DWPCI MacroCell from Synopsys? Was it
> compliant with the relevant specifications? What were the implementation
> issues? How did you handle the I/O timing (PLL, etc.)? Thanks for any
> information you can supply.
>
> - Dave Peeters
> Entridia
From: Jim McDonald <jim@3ware.com>
Hi, John,
I'm not sure what the correct form this should take; here are the points we
used to choose the DW PCI core:
1) Performance: The DW PCI core is able to initiate fast back-to-back
transactions and memory write and invalidate commands. Other core
designs insert or require extra latency clocks or turn-around (recovery
time) clocks. These limitations do not seem to exist in the DW PCI
core. Some of the cores that we looked at were designed years ago and
didn't seem to optimize performance.
2) Ease of integration: The DW PCI core comes with an extensive simulation
environment that allows regression testing of PCI compatibility. Also,
since the DW PCI core comes from Synopsys, it seems to optimally use DC
to generate scripts that correctly enforce PCI timing requirements.
This feature gave us confidence that we could meet PCI specs with
readily available silicon processes.
3) Flexible: The same core design is usable for 32/64 bit and 33 MHz or 66
MHz. Also, many parameters are configurable at synthesis time, without
re-writing verilog code.
4) Documentation: The documentation is comprehensive (huge) and seems
complete. This docmentation includes PCI & back-end waveforms instead
of just text descriptions, helping to visualize the transactions.
We have used some other PCI core designs that were more limited and less
complete. For example, one core we have experience with does not perform
any of the initiator retry functions automatically; so back-end logic must
be created and verified to meet the PCI specification (i.e. we had to
become PCI experts to make this core work properly.)
Our design is not in silicon yet, but we have done some simulation and
back-end design. We're very optimistic about making our design goals.
- Jim McDonald
3Ware Palo Alto, CA
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