( ESNUG 330 Item 3 ) --------------------------------------------- [9/30/99]
Subject: ( ESNUG 329 #11 ) Tools To Convert Transistors Into Schematics
> Has anyone ever heard of a tool that can convert a transistor-level SPICE
> netlist into a schematic? We thought about making a dummy library in
> Library Compiler and then converting the netlist into verilog then reading
> it in to DC, but there has to be a better way. Any ideas?
>
> - Andy Frazer
> Integrated Device Technology Santa Clara, CA
From: [ Life In The Fast Lane ]
John, keep me anonymous.
There are two tools that I know of -- Cadence's Affirma_TLA (Transistor
Logic Abstractor), and Tuxedo-LTX from Verplex.
- [ Life In The Fast Lane ]
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From: Benoit.Durand@st.com
John,
When I was AE at COMPASS, we had a tool called 'Laybool' that was able to
convert SPICE netlist to Verilog or vhdl. I think that Avanti still sells
this tool. It's new name is Lynx.
- Benoit Durand
ST Microelectronics
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From: David Chapman <dchapman@aimnet.com>
John,
If this user wants extract the functionality of the cell and generate a
truth table, there are two ways to look at the problem:
1) lots of library characterization tool vendors perform this step
automatically as part of the delay measurement process
2) it is very difficult because of issues with dynamic logic,
pass-gate logic, and feedback cells (i.e. flip-flops)
These are not contradictory; the tools tend to fall down when given "messy"
cells. He may need to hire some outside help to do this tranlation by
hand or, of course, the library characterization vendors would be only
too happy to help you -- for a price.
- David Chapman
Chapman Consulting Santa Clara, CA
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