( ESNUG 329 Item 3 ) --------------------------------------------- [9/22/99]
Subject: ( ESNUG 327 #3 328 #4 ) Metastability 'Z' In Some Xilinx FPGAs
> Metastability 'Z' is no more of an issue in an FPGA than it is anywhere
> else. For Xilinx FPGAs, Greg's comment about lookup tables is incorrect.
> I don't know the situation for other vendors.
>
> The way it works is as follows:
>
> Let's assume that we have a 4 input LUT, implementing a 2 input and gate.
> Of the 4 inputs (address lines to the lut), two are grounded (i.e. never
> change) and the other two select 1 of four locations. The locations
> depend on which two address lines are used. Of the 4 locations that are
> interesting, three are set to '0', and 1 is set to '1'. Unlike RAMs or
> other memory structures with word lines, bit lines, sense amps,
> pre-charge, and other entertainment, the LUTs are implemented as latches,
> 16 of them. They then connect through a tree of pass transistors to the
> output.
>
> Regardless of which single input is changing, only 2 of the pass
> transistors in the tree are involved in the change over from one value to
> the next. Since the outputs of all the 16 latches have propagated through
> the tree as far as they can, when you change over from one location to
> another (with only 1 address line changing), and both have the same value,
> the transition does not cause a glitch in the output.
>
> If you care, you can see this structure on page 4 of:
>
> http://patent.womplex.ibm.com/cgi-bin/viewpat.cmd/US04870302__
>
> Clearly, if both inputs are changing, a glitch could occur, but then the
> same is true of a real AND gate.
>
> Although my example is for a 2 input gate, the same is true for 3 or 4
> input structures that are mapped to a LUT. The basic rule is that if
> only one input is changing, and both the before and after values are the
> same, no glitch can occur.
>
> While somewhat more difficult to describe, it can be shown that for
> structures like a 3 or 4 input AND gate, with one input held low, you can
> have multiple of the remaining inputs changing simultaneously, and not
> get glitches in these situations either.
>
> - Philip Freidin
From: Greg Dean <Greg.Dean@nsc.com>
Hi, John,
The Xilinx circuit Philip refers to uses a tree of NMOS pass transistors
forming a 16 to 1 multiplexor to do the selection for the lookup table.
Indeed this configuration is able to safely implement an AND or NOR (one
input can select between two lows without glitching). However, when
switching between two highs (as in a OR or NAND gate), the output may
glitch low, especially if the input is near threshold for an extended
period of time, such as when the input comes from a metastable latch.
Consider the following section of the circuit. With the A input in the
center of the inverter's threshold (assume VDD/2), the output, A# is also
at VDD/2. This puts OUT at VDD/2 - Vth, which is below the threshold of
the buffer, and so OUT_buf is low.
A -------+---|>o----+ A#
| |
_|_ | OUT
VDD ----------------)------+-------|>--- OUT_buf
| |
_|_ |
VDD -----------------------+
There are other (off) transistors not shown connected to OUT which
contribute some leakage current to this node to pull it down.
In normal usage, this should not be a problem, as stored charge on OUT
should hold its voltage while the A input quickly switches through this
region of operation.
- Greg Dean
National Semiconductor South Portland, ME
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