( ESNUG 328 Item 9 ) ----------------------------------------------- [9/9/99]
Subject: ( ESNUG 327 #12 ) In Attempting To Synthesize Fixed Time Delays
> To the best of my knowledge, I've never seen a delay element like this in
> a standard FPGA or ASIC device. If there was one, then you could use VHDL
> to synthesize it.
>
> Most people use one of the two following techniques to solve this problem:
>
> 1) Design your circuit assuming that all gates and nets have a very small,
> but non-zero delay time. For example, you can design a reliable
> synchronous circuits w/o the use of delay elements of any kind. For
> examples of this, you can refer to our 'WISHBONE' interconnection
> system on our website at http://www.silicore.net
>
> 2) If you really need a delay element, then you can add one external to
> the part. There are quite a few companies that make delay line
> devices, which give very precise timing delays. Kappa, Delay Devices
> and Dallas Semiconductor are a few companies.
>
> Also, you can make your own very predictable fixed delay elements with
> inductor/capacitor parts.
>
> - Wade D. Peterson
> Silicore Corporation Minneapolis, MN
From: "D. M. H. Walker" <walker@cs.tamu.edu>
John,
On item 12, respondents implied perhaps inadvertently that fixed delays
are not available on chip. Many papers have been published on accurate
on-chip delay lines, most commonly used in clock and communications
circuits. They typically require referencing to a known clock via a phase
or delay locked loop, which is probably way more circuitry than the
requestor desired. Just adding some extra gate delays and hoping for
appropriate tracking is the way to create bad designs. A recent IEEE
Circuits and Devices magazine article discussed timing chains as commonly
used in memory arrays. It did not adequately address process variation, but
gives a starting point. I would say that at the RTL or logic design level,
you cannot get closer to a target delay than +/- 30% of one typical gate
delay, and if you don't have lots of vendor data you could easily do much
worse. Since presumably the requestor is interested in tracked delays than
absolute delays, they might do better by putting several gates in parallel
and making sure they are spread out during P&R so as to average the
intra-die process variation. But in general such designs have poor
manufacturability unless they were done using detailed knowledge of the
physical design and manufacturing process, i.e. not an ASIC design flow.
- Duncan M. (Hank) Walker
Texas A&M University College Station, TX
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