( ESNUG 328 Item 7 ) ----------------------------------------------- [9/9/99]
From: Lou Villarosa <louv@paradyne.com>
Subject: Can I Prevent DC From Replacing The Original Cell Instance Names?
John,
In my design .db, I have cell names like "counter_reg(0)". When I write out
the design to VHDL for gate level simulation, the instance name changes to
"counter_reg_0_label".
When I try to back annotate the SDF file from the traget vendor in my VHDL
simulator, I encounter errors because the SDF file used the original cell
name, "counter_reg(0)".
How do I prevent Synopsys from replacing the original cell names?
- Lou Villarosa Jr.
Paradyne Corporation
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