( ESNUG 328 Item 6 ) ----------------------------------------------- [9/9/99]
Subject: ( ESNUG 326 #4 ) So Called "DesignWare Wireload Bug" Demystified
> I've found that Design Compiler generated hierarchy (i.e. DesignWare) gets
> the wrong wireload model. I've run into this using 1998.98-1, but I
> checked the problem with 1998.02-2 and 1999.05 and got the same results.
> When using enclosed wireload models, generated DesignWare hierarchy gets
> the wrong wireload. If there is a default_wire_load attribute in the
> library, that wireload is used. If there is no default_wire_load
> attribute set, NO wireload is used. ...
>
> - Bob Wiegand
> Ensoniq Corp. Malvern, PA
From: [ A Synopsys CAE ]
To: Bob Wiegand <rwiegand@ensoniq.com>
Bob,
I might be missing something, but I thought this is the way it's supposed
to work? I believe the order is this when using 'enclosed' wireloads:
1. specifically set wireload, if any
2. wireload chosen from auto_wire_load_selection, if enabled
3. wireload from library default_wire_load, if any
4. first wireload encountered up the design hierarchy
In other words, if there is NO wireload set on the design, it will inherit
it from the next lowest-level enclosing design with a wireload. This means
that if you have no default_wire_load and no auto_wire_load_selection,
synthetic ops will inherently use the parent wireload when they come into
creation during compile! However, doing a report_design on that DW will
still report there's "no" wireload, because there indeed isn't one
explicitly set.
I did a real quick test setting the top level of a design to a certain
wireload, with all the subdesigns having no wireload. The results were the
same as setting all designs to that same wireload. The timing for having
no wireload whatsoever set was different, so this supports that designs
with no wireload do indeed inherit them from parent hierarchy.
- [ A Synopsys CAE ]
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From: Bob Wiegand <rwiegand@ensoniq.com>
To: [ A Synopsys CAE ]
I agree with the order you present for wireload selection in enclosed mode,
but have to question the order of 3 and 4. I would think you want the
first wireload encounterd up the hierarchy to take effect first, and then
if all else fails use the default_wire_load from the library. Anyway, the
situation with designware was slightly different. I went out of my way to
specify the wireload on the generated designware, and DC went out of it's
way to ignore that information. The thing that led me down this path in
the first place was an OPT-170 message, telling me that the wireload for a
particular DW component was changed from "none" to a 1M gate wireload which
turned out to be the default_wire_load for that library.
I decided to go back and check my facts using two diffent libraries,
compiling a small design without ungrouping the designware hierarchy and
then doing a report_timing on that design. Here's what I found:
Condition 1: No library default_wire_load,
auto_wireload_selection = false.
OPT-170 message: no message
Timing Report: designware not shown
Condition 2: No library default_wire_load,
auto_wireload_selection = true.
OPT-170 message: none to auto-selected
Timing Report: shows designware with auto-selected wireloads
Condition 3: Library default_wire_load present,
auto_wireload_selection = false.
OPT-170 message: none to library default
Timing Report: shows designware with library default wireloads
Condition 4: Library default_wire_load present,
auto_wireload_selection = true.
OPT-170 message: none to library default,
library default to auto-selected
Timing Report: shows designware with auto-selected wireloads
Condition 5: Implementing fix from ESNUG 326 so that library
default_wire_load is equal to parent design wireload,
auto_wireload_selection = false.
OPT-170 message: none to parent wireload
Timing Report: shows designware with parent wireloads
Condition 6: Implementing fix from ESNUG 326 so that library
default_wire_load is equal to parent design wireload,
auto_wireload_selection = true.
OPT-170 message: none to parent, then parent to auto-selected
Timing Report: shows designware with auto-selected wireloads
For condition 1, I tried ungrouping and then report_timing again. The
timing did not change, indicatating that the designware inherited the
parent wireload as you said. After ungrouping and retiming the other
conditions, the timing changed as expected to indicate the designware was
indeed using the reported wireloads.
I previously reported that the auto_wireload_selection value didn't change
the result, but here it obviously did. These results support the order you
specified. I am surprised to find the library default_wire_load has a
higher priority than the parent design's wireload. Condition 1 and
Condition 5 both seem to get around the problem. I prefer to see the
hierarchy and their associated wireloads as they occur in Condition 5.
- Bob Wiegand
Ensoniq Corp. Malvern, PA
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From: [ A Synopsys CAE ]
To: Bob Wiegand <rwiegand@ensoniq.com>
Bob, just a summary of my experiences from what we discussed:
When you are doing hierarchical compiles, paying attention to how wireloads
are applied throughout the hierarchy is very important. When you synthesize
a design from RTL, any inferred operators (DesignWares) "pop" into existence
during synthesis. Here is how their wireload model is inferred:
* if the wire_load_mode of top is used, the wireload of the
current_design is used, else
* if auto_wire_load_selection is enabled, a wireload is selected
based on area, else
* if a default_wire_load exists on the target_library, this
wireload is used, else
* the wireload of the first parent design with a wireload is used.
Note that in the last case, you will see no wireload when you do a
report_design on these subdesigns. The wireload is not explicitly set when
it inherts; rather, it inherits dynamically. Ideally, you normally want
DesignWares to use the wireload of their parent. This means that you must
set auto_wire_load_selection=false in your DC setup, plus you must remove
any default_wire_load attributes from your libraries after you link:
remove_attribute find(library) default_wire_load
Once this is done, you can simply set a mode of enclosed, and set the
desired wireload on the current_design and any subdesigns. From these
user-specified designs down, the wireload will be propagated automatically.
If this is the desired methodology, it's advisable to set
auto_wire_load_selection=false
in your .synopsys_dc.setup, and use read_db/remove_attribute/write_lib to
create custom libraries without any default_wire_load. Then, this flow is
totally transparent.
- [ A Synopsys CAE ]
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