( ESNUG 325 Item 5 ) ---------------------------------------------- [8/18/99]
Subject: SDF Annotate Verilog-XL Issues w/ Mixing Two ASICs From Two Vendors
> I am working on a project in which I am designing a support ASIC
> for another, separate ASIC based on an ARM7 core.
> I decided to link these two ASIC's together in one Verilog test
> bench to see if they'll work together the way I think they should. The
> two ASIC's are being fabricated by two different vendors (I'll just
> refer to them here as Vendor A and Vendor B) which naturally means that
> they have two different sets of library files to use. However, there
> are a number of cells in these two libraries that just happen to have
> the same names (e.g. the names of the 2-input NAND gate cell and the 3-
> input OR gate cell are identical in both libraries).
> The first problem I had was that Verilog-XL would try to build the
> support ASIC out of vendor A's library components instead of vendor B's
> library. I was able to solve this problem using the `uselib directive.
> Verilog-XL now looks at the correct library for each device when
> compiling the files. The current problem is with the SDF annotation. I
> can get the ASIC with the ARM core to annotate without a problem. But
> when I try to annotate the support ASIC, I get the following error
> messages reading SDF file and back-annotating timing data...
>
> /proj5/osa/vendor/postimp/pre_asa.sdf
> L773: SDFA Error: Type of INSTANCE (...).u10
> (or3$inst3_8$3) does not match CELLTYPE or3
>
> /proj5/osa/vendor/postimp/pre_asa.sdf
> L1027: SDFA Error: Type of INSTANCE (...).u204
> (nd2$inst3_8$3) does not match CELLTYPE nd2
>
> ...(and so on for a total of 123 SDF annotator errors on a couple of
> different cells)
>
> It appears to me that it's trying to annotate the support ASIC's
> data using the library of the ASIC with the ARM core. I don't get these
> error messages when I annotate the ARM core. I used the $sdf_annotate
> task to invoke the annotator in my test bench before doing any
> simulations, and I did tell it specifically which instance should be
> annotated from which file.
>
> Anybody have any ideas? I can run simulations without the
> annotation on the support ASIC, but I'd really like to make this as
> accurate of a simulation as I possibly can.
>
> - Greg Arena
> Dialogic Corporation Parsippany, NJ
From: "Ashutosh Varma" <ashu@axiscorp.com>
I think maybe because of `uselib, the cell defnames have been changed by
Verilog-XL to make them unique. And your original SDF file doesn't expect
this change.
I do not see an easy way out of this, except writing a script to manually
make the module names different for both libraries (prefix with something)
and the corresponding SDF files. With that, you can avoid having to use
`uselib.
- Ashutosh Varma
Axis Systems Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: paulge@pwrtool.cse.tek.com (Paul Gerlach)
This is true. I haven't used `uselib for a couple years, but I think I
remember this. I have the following line in a -f file, give it a try:
+sdf_nocheck_celltype //sdf doesn't work with uselib without this
Concerning Greg's "INSTANCE (...).u10 (or3$inst3_8$3) does not match
CELLTYPE or3" problem: when in doubt, turn it off!
- Paul M Gerlach
Tektronix, Inc. Beaverton, OR
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