( ESNUG 325 Item 1 ) ---------------------------------------------- [8/18/99]
Subject: ( ESNUG 324 #1 ) Avanti Timing-Driven P&R Clashes With Synopsys Use
> Recently there were some disgruntled Avanti customers complaining about
> Avanti licensing procedures in ESNUG. I just thought I'd add to this
> discussion by letting everyone know this creative licensing isn't just
> reserved for their HDL RTL tools.
>
> In the Avanti P&R system you can add numerous options. These include
> HPO (high performance option), power analysis (Mars Rail), physical opto
> (Saturn), cross-talk (Mars Xtalk), and timing driven. They utilize the
> flexlm licensing so each of these options have a unique set of tokens
> associated with each of them.
>
> - [ The Man In The Iron Mask ]
From: "Manish Shrivastava" <manish@ieee.org>
Hi John,
Recently I heard a term called Power driven layout and I literally laughed
at the people who told me that. But after reading this ESNUG I think I
should have not done that. It looks like Avanti does support some kind
of Power analysis built into the tool. But does this mean that Avanti
can support some kind Electromigration / IR drop driven layout?
Does this also mean extra effort on Libraries to be characterized?
Currently, we just use the Timing Driven feature of Avanti P&R and it
turned out to be a nightmare because our frontend designers love the path
segmentation feature of Synopsys and they create a false path from any
point to any point by just creating a hierarchy there. Then when you go to
the Avanti backend tool you have to dig out each net, or cell Input/Output
and tell it to disable timing through it. OK, it is similar to doing it
in the front end, but then you have hierarchy in front end, and a flattened
verilog netlist at the backend.
I hope the Avanti Static Timing Analysis tool can start supporting something
more then just the CLK pins / input ports and D pin of FF / output ports for
its start and end points.
Oh, I would like to share a trick with everyone, may be people know about it
already. To break a path through the bidirectional ports in your design,
you can now happily use the -through option in Synopsys. What you need for
Avanti is just to find the instance name of the tristate driver and the
input side buffer and use the command tdfSetDisableTiming ( output of
tristate buffer, input of the input side buffer ) and you have a false path
set for breaking the false loop. But beware, not related to above but to
bidi port, never declare a port as bidi unless you are driving and
recieving data -- else Avanti just removes a bidi port with connection to
one direction only from your slack graph.
- Manish Shrivastava
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