( ESNUG 324 Item 16 ) --------------------------------------------- [8/04/99]
Subject: The Software Engineers Liked That We Used 'Virtual CPU' From Summit
> Hi. I would like to read the impression of people who used Virtual CPU
> from Summit Design.
>
> - Yoram Stern.
From: dlsnell@my-deja.com ( Dorian Snell )
I have used VCPU for about 6 months on an ARM based project. We brought it
into the design flow late in the cycle and have been very pleased with
the results. We are a small team on a very complex chip and VCPU has
improved our productivity in two ways:
1. It reduces our simulation overhead because the ARM is not using
up cycles in our verilog simulator.
2. It removed a step in our simulation process by allowing us to
run code on a code debugger directly against the verilog (which
the sw guys like), instead of converting it to a binary image for
loading to a verilog memory model for simulation.
Perhaps more importantly, our customer (software developers) likes it
because they can develop code on their own tools in another state and
run it on our verilog with minimal interference from us (sensitive IP
issues). In my opinion, VCPU contributed significantly to our ability
to deliver functional prototype silicon to our customer ahead of their
expectation.
VCPU is not perfect, it has some inherent timing quirks because the code
is not executed on the simulation clock (bus cycles are). However, we
are aware of those issues and have not seen any problem related to them
so far.
- Dorian Snell
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