( ESNUG 322 Item 9 ) ---------------------------------------------- [6/15/99]
Subject: ( ESNUG 317 #10 ) The Scoop On The Remade DesignWare PCI Module
> Synopsys re-introduced a synthesizable PCI core in the DesignWare library
> last year. Have you heard from any one that used it? Now it's in the
> DW Foundation library. I heard the first version was difficult to use
> (even Synopsys admited that), and the new version is much better. Is this
> true? I'd appreciate any info you can pass to me.
>
> - William Liao
> MMC Networks
From: Richard_Grenier@3com.com (Richard Grenier)
John,
We've used the new Synopsys DW PCI core in a recent product. It was a
complex PCI configuration that needed to support both 32 and 64 bit
configurations and run at both 33mhz and 66mhz {4 corners}. Our first
implementation was in 3.3v 0.35u 3LM.
We recently received the silicon and have had zero bugs in the PCI front-end
of the chip. All PCI transactions on both 32 and 64-bit buses, as well as
33 and 66 Mhz have been thoroughly tested and are functional. The NIC
itself is already running Netware & NT drivers, as well as diagnostics.
The PCI core has been exposed to a variety of 32 and 64 bit bridges, as
well as 33 and 66 Mhz operation. We do feel, however, that use of a PLL to
compensate for insertion delay is recommended for 66 Mhz PCI operation over
the full commercial temperature/voltage ranges, though this is a
technology-specific constraint.
On the technical support side Synopsys was attentive to our needs and issues
throughout the course of the project.
- Richard Grenier
3Com Santa Clara, Ca
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From: "Joerg Landmann" <lama@de.xionics.com>
John,
Recently, we began development of a full featured PCI interface to work with
a multifunction device. By using the PCI bus to connect various interfaces
with a general purpose CPU, the decision was made to exploit a ready-to-use
core from an IP vendor. The group had already started the design process
using a core from a different vendor when we became aware of the Synopsys
DW PCI. Granted, there were strong reasons to use that prior IP core
in the first place (proven silicon), but the Synopsys approach was different
enough to warrant another evaluation cycle.
We decided to switch to the Synopsys DW PCI core because it had a:
- Very easy-to-use installation procedure
- Easy GUI-driven configuration mechanism
- Automatic generation of simulation model together with a
ready to use compliance test suite
- Automatic generation of the synthesis models together with
ready to use synthesize scripts for the Design Compiler
Of course, the installation alone didn't provide a workable product, but it
helped us make certain design decisions very early in the process. Our ASIC
uses NEC's CBC9VX 0.35 micron technology and the 32bit PCI bus is running
at 33Mhz. The overall gatecount of the ASIC including the PCI interface
is about 250K gates.
After generating the core, the group was able to synthesize the complete
core (including the pads) to a timing-clean netlist containing all the
functionality we had defined, and in less than a 1/2 day.
This shortened development cycles enabled us to test various configurations
(like different numbers of BARs, ...) prior to designing the application
interface. Each configuration was tested within the PCI compliance test
suite, which offers an indication of the (PCI) design's quality without
having to worry about writing big chunks of test code.
Besides the installation and startup procedure, the seamless interface of
synthesis and simulation environments drove the final decision to implement
the PCI interface as a "DW PCI core" into the design.
While the Synopsys approach providing the PCI IP is novel, we experienced
a couple of problems in the design cycle, but none of them were fatal:
- The installation tree is complicated. Updates to the simulation
environment as well as the Design Compiler scripts are not intuitive.
- The target library should support the scan process with the GUI of
the DWF software. If it does not, all PCI pads may not be found.
During our design process, we found that the PCI interface needed to grow
with our needs and add functionality to the ASIC. There was a clear need
to support a multi-function PCI interface to enable plug and play for
multiple interfaces located on the device, while the DW PCI core remained
single functioning. Additional Synopsys documentation helped us make
modifications primarily to the top level macro to support additional
function units. This process greatly impacted our plans for future
projects. While the design supports functionality, it is not yet completely
defined. If the PCI requirements change, it will be important to have the
flexibility to switch to a source code model which fits seamlessly into an
existing DWF library.
- Joerg Landmann
Xionics Dortmund, Germany
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