( ESNUG 322 Item 4 ) ---------------------------------------------- [6/15/99]
Subject: Cadence Pearl Static Timing Analysis Interface Has Improved
> How I can make a static timing analysis (critical path extraction) with
> Cadence's 97A version? We are in Cadence Virtuoso with the routed view
> of the circuit (after a P&R). I can extract SPF, SDF... but if try to
> calculate all delays .... the window not show any path (delay).
>
> - V. Puente
From: Ed Chester <ed@chester.net>
You can use Pearl, the command-line based unfriendly tool included with
Cadence 97A onwards. It is actually a pretty powerful static timing
analyser that doesn't need stimuli, but it's horrible to use. Read the
on-line documentation in "Openbook" about it: IC Tools, Timing Analysis,
Pearl. You're on the right track, you need the SDF/SPF and whatnot.
- Ed Chester
University of Newcastle UK
---- ---- ---- ---- ---- ---- ----
From: Alan Barclay <abarclay@terasystems.com>
I can't say as to when (or whether) it will be released, but I was
working on integration of Cadence's Design Planner with the Pearl GUI when
I was laid off from Cadence in Nov98. The Pearl GUI was also being
integrated with Silicon Ensemble.
The Pearl GUI was a pretty nice piece of work, written in Tcl/Tk, allowing
you to winnow through the possibilities according to various criteria,
then display each one with both a tabular view of the delays, and a
drawn-on-the-fly schematic. Massive usability improvement...
- Alan Barclay
Tera Systems
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