( ESNUG 322 Item 1 ) ---------------------------------------------- [6/15/99]
Subject: ( ESNUG 319 #8 321 #3 ) Disgust At The Avant! VeriLint 'Upgrade'
> Although perhaps not quite as strongly as Sparticus, I also object to the
> way Avant! is handling the InterHDL/Verilint "upgrade". We have three of
> the hold time licenses and have found them useful in our design flow.
>
> I have tried to explain to Avant! that the tool is not a $45K tool, but
> they seem unmoved. I wonder how many of their customers are really going
> to take them up on their offer to upgrade, and how many are going to go
> with a permanent key, drop maintenance, and not give them another dime?
>
> It is particularly annoying that they want to charge maintenance based on
> the $45K price of the tool. This means our yearly maintenance would be
> almost $7,000 --- what we paid for each license originally.
>
> It looks to me like their strategy is to move their Verilint customer base
> to their Nova-Explore-RTL product. This product requires you to run
> interactively in a multi-window GUI type environment. Just like every
> other EDA vendor, they want to have the Holy Grail of EDA Software. That
> is, a tool that a designer is going to sit in all day long while doing code
> development and debug. I don't think Nova-Explore-RTL is it.
>
> - Tom Loftus
> Hughes Network Systems
From: [ The Man In The Iron Mask ]
John,
I thought I'd bring to your attention a couple of more issues about the
Avant! Verilint powerplay. Politics say I must remain anon.
1) Avant! warned me:
"YEAR 2000: Nova-Verilint 4.3 uses FLEXlm Version 5.12b and is fully
Y2K compliant. Older versions of our [Avant!'s] software (which uses
the Elan license manager Version 4.x) have a known minor Y2K problem
in the ilmrpt license usage reporting utility"
This is a clever ploy by Avant! who realizes that it may be less
hassle for me to pay the upgrade fee than to explain to my management
how I'm going to remain Y2K compliant. Y2K compliance folks tend not
to want to hear: "its only a useless reporting utility that's affected"
2) Avant! also warned me:
"Verilint-XL has a unique feature that 'holds' a license for a
particular user for a 27 minute period. Having moved to the FLEXlm
license manager, this type of Verilint license is no longer
available."
This feature is hardly unique. This feature is available with FLEXlm
as "linger" and was implemented by BSO Tasking a Dedham, MA vendor of
RISC compilers. For the information for your users, both Elan and
FLEXlm treat a "user" as a username/hostname/DISPLAY value 3-tuple.
So if you want to "fake out" the license, you need to keep all three
the same.
Free enterprise and competition is the only way to keep Avanti "honest"...
(and okay the Cadence people can stop laughing now.) A colleague passed on
to me the following URL for a Verilint competitor. I do not have any
experience with this product but would be interested in feedback from any
of your readers on ESNUG who do: http://www.dualsoft.com/reviewver.htm
- [ The Man In The Iron Mask ]
---- ---- ---- ---- ---- ---- ----
From: Billy Vitro <bvitro@cisco.com>
John,
I just saw an ad for the Proton Rule Checker -- a lint-like tool from ASC
Inc. (http://www.ascinc.com), and was wondering if anyone else had used it
and what they thought of it in comparison to Verilint. It looks like it's
time for capitalism to fix this little problem.
- Billy Vitro
Cisco
---- ---- ---- ---- ---- ---- ----
From: "Janick Bergeron" <janick@qualis.com>
John,
If you were using Verilint solely as a syntax checker, than you were missing
it's most useful feature: a LINTER.
I recommend using linter as the *first* line of attack in debugging Verilog
models. I have *personally* run Verilint only on a large RTL model
(synthesized to 2.2M gates) for two weeks and found and fixed between 3 to
8 *functional* bugs a day, without running a *single simulation cycle*.
The RTL model was not even close to be simulatable (someone else was getting
the simulation environment ready during those 2 weeks). In my book, that
comes out as more valuable than the simulator in terms of productivity.
It is still beyond my understanding why anyone would find Verilint expensive
at $47k for what basically becomes a site license. It pays for itself, in
terms of engineering productivity, during a single ASIC project. My
recommendation: cough up the upgrade cost but demand the new features (such
as configurability) that will be found in Nova...
One thing engineers have to realize: these tools cost money to develop and
maintain and one should expect returns according to the *benefit* they
provide. With a tool that runs in seconds, a useage-based licensing that
has historically worked in the EDA industry does not work: a single license
will support any number of users. Why should a company with 150 engineers
using that license pay the same thing as the 3-engineer start-up? They are
getting 50x the benefit. Qualis faced the same decision with VMK, our
makefile generator for VHDL models -- and came up with a similar solution
(albeit marketted differently as a 'day-user': the license is held until
midnight).
Globetrotter uses a different model: the more money you make selling the
tool licensed using their product, the more it costs (e.g. Synopsys
may pay $1M for the *exact* same software we paid $7,500 for -- but they
are getting a *lot* more benefits from it than we do). The customer's
(mis)perception of a held license forced Avanti to try to change their
model... to everyone's apparent disadvantage. Be careful what you wish for.
Of course, a little bit of competition in the linter field would be welcomed.
> It looks to me like their strategy is to move their Verilint customer base
> to their Nova-Explore-RTL product.
They are not shy about this. A rep told me exactly that in their booth at
HDLcon last April. Personally, I'll take a command-line batch tool over
an interactive GUI any time....
BTW, while I have your attention... does anyone else find "// verilint #
on/off" cumbersome and dangerous? Not only does it clutter your code with
two directives for each check you want to turn off, but creates a region
where a check can be inadvertedly left OFF. I suggested to Eli long ago to
have a "shut up for this line only" directive:
someVerilog code here; // verilint # ok
And be "sticky" to the object when put on a declaration
reg [4:0] my_state; // verilint ... ok ( Turn off warning about
inferred FF)
Never seen that feature make it in....
- Janick Bergeron
Qualis Design
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