( ESNUG 321 Item 10 ) --------------------------------------------- [6/8/99]
Subject: ( ESNUG 319 #3 ) Accessing Intermediate Bits In Module Compiler
> I have been given the task of evaluating Module Compiler. After cruising
> along the learning curve quite well, I came to a roadblock. The ALU
> datapath I was implementing as a test case had the use of intermediate
> carry bits from the 32-bit adder. I have yet to find in the documentation
> how one gets access to these bits or if it is even possible. Any help
> from ESNUG would be appreciated.
>
> - Barry Williams
> Rockwell Avionics
From: [ A Synopsys Module Compiler AE ]
Hi John,
Here are some examples that try to illustrate how to access carry signals.
Barry's problem (we spoke on the phone) is to get access to the carry signal
after each successive 8 bits in the sum. Really, this is just breaking down
a big 32-bit adder into 4 8-bit adders and connecting the carry-out from a
lower 8-bit adder into the carry-in of the next higher 8-bit adder. This
can be easily accomplished with the following code example done both for
unsigned and signed. Note that this will be slower than the full 32-add
because we can only do fast-carry-look-ahead for 8 bits at a time instead
of all 32 bits.
This is the UNSIGNED reference design:
module add_slice_ref(a,b,y);
directive(delay=10000);
input [31:0] a,b;
output [32:0] y;
directive(fatype="csa"); // I chose "carry select adder"
// architecture for the adder type.
y = a + b;
endmodule
This is the UNSIGNED carry access design:
module add_slice(a,b,y);
directive(delay=10000);
input [31:0] a,b;
output [32:0] y; // output needs to be 33 bits for no overflow.
// bit 32 is the carry-out.
wire [8:0] y3,y2,y1,y0;
directive(fatype="csa");
y0 = a[7:0] + b[7:0];
wire [1] c8 = y0[8];
y1 = a[15:8] + b[15:8] + c8; // y0[8] is the carry out
// from the first 8 bits
wire [1] c16 = y1[8];
y2 = a[23:16] + b[23:16] + c16; // y1[8] is the carry out
// from the second 8 bits
wire [1] c24 = y2[8];
y3 = a[31:24] + b[31:24] + c24; // y2[8] is the carry out
// from the third 8 bits
y = cat(y3,y2[7:0],y1[7:0],y0[7:0]); // y3[8] = y[32] is the
// carry out from the
// last 8 bits
wire [1] c32 = y3[8];
// Now you can use the carry for your particular use
endmodule
This is the SIGNED reference design:
module add_slice_signed_ref(a,b,y);
directive(delay=10000);
input signed [31:0] a,b;
output signed [32:0] y;
directive(fatype="csa");
y = a + b;
endmodule
This is the SIGNED carry access design:
module add_slice_signed(a,b,y);
directive(delay=10000);
input signed [31:0] a,b;
output signed [32:0] y; // output needs to be 33 bits for no overflow
wire signed [8:0] y3;
wire unsigned [8:0] y2,y1,y0; // only y3 contains the signbit.
directive(fatype="csa");
y0 = a[7:0] + b[7:0];
wire [1] c8 = y0[8];
y1 = a[15:8] + b[15:8] + c8; // y0[8] is the carry out
// from the first 8 bits
wire [1] c16 = y1[8];
y2 = a[23:16] + b[23:16] + c16; // y1[8] is the carry out
// from the second 8 bits
wire [1] c24 = y2[8];
y3 = a[31:24] + b[31:24] + c24; // y2[8] is the carry out
// from the third 8 bits
y = cat(y3,y2[7:0],y1[7:0],y0[7:0]); // y3[8] = y[32] is the
// carry out from the
// last 8 bits
wire signed [1] c32 = y3[8]; // Note that this is also
// the sign bit
endmodule
Also note that I wanted to verify my coding, so when I also created a simple
32 bit adder of each flavor (signed and unsigned), I used Formality to
quickly check the output of Module Compiler that the versions with carry
bit access are 100% functionally equivalent.
- [ A Synopsys Module Compiler AE ]
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