( ESNUG 321 Item 8 ) ---------------------------------------------- [6/8/99]
Subject: ( ESNUG 316 #3 320 #10 ) Transmission Gates Ruin Fault Coverage
> As a former Sunrise/Synopsys Test CAE/Consultant, this issue is fairly
> common on custom designs that use fully-decoded N-input muxes. Modeling
> these with bufif1 primitives is fine for TestCompiler or TestGen. This
> is more fundamental to the stuck-at fault model & this type of circuit...
>
> ... If the decoder and mux combination can be re-modeled as a single,
> encoded mux cell, a complete set of patterns will be generated and a full
> coverage will be reported.
>
> - [ A Former Sunrise/Synopsys Test CAE/Consultant ]
From: Subhasish Mitra <smitra@CRC.Stanford.EDU>
Hi John,
It's not clear whether it is suggested that the designer replaces the
decoder and the decoded multiplexer (selector) by an encoded mux IN THE
DESIGN. If the decoder and the selector combination is modeled as a fully
encoded mux just for the purpose of testing (i.e. for the ATPG tool),
then the set of patterns generated will only test for stuck-at faults at the
pins of this decoder-selector combination -- thus, the actual stuck-at
faults at the selector select signals will not be considered -- So in that
case, the fault coverage reported will NOT be the actual fault coverage.
(Note that the actual stuck-at fault model is defined as stuck-at faults at
inputs and outputs of basic gates. Basic gates are AND, OR, AND, NOR and
inverter. Even for 2-input XOR gates a THOROUGH test requires 4 patterns
instead of 3).
Testing for select inputs of decdoed mux-es represents one aspect of the
problem. How about ensuring one-hot values on one-hot signals? This problem
may be handled if a good ATPG is used and some logic is added to ensure
one-hot values during scan-in and scan-out. BUT WHAT HAPPENS DURING A
PSEUDO-RANDOM BIST or RANDOM PATTERN TEST? Any suggestions?
- Subhasish Mitra
Stanford University
---- ---- ---- ---- ---- ---- ----
> I recommend replacing the entire mux model with a model of the cell that
> only uses ands, ors and inv's. Completely ignoring the internal structure.
> And suppress faults inside the cell. The "stuck-at" model is still valid
> at the pins of the cell.
>
> - Gary Porter
> Harris Semiconductor
From: Howard Landman <HowardL@SiTera.com>
John,
One advantage of this style of mux model (as opposed to a behavioral "if" or
"?:" model) is that it will propagate X values. (The Verilog language spec
requires an if statement to treat an X as if it were a 0.) However, there's
a subtlety that many people miss. You want it to be the case that, if your
select is X, but both data values are the same, then the output is the data,
not X. (You can trust me on this, or learn from painful experience. :-)
Therefore, your mux models need to include a "redundant" term. Here's an
example (the "a & b" term is redundant for 0-1 values):
module mux2 (z, a, b, s);
output z;
input a, b, s;
reg z;
always @(a or b or s)
begin
// redundant term to get correct behavior when s is X .
q = (~s & a) | (s & b) | (a & b);
end
endmodule
I *STRONGLY* recommend all behavioral mux models be written in this manner.
- Howard A. Landman
SiTera, Inc. Longmount, CO
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