( ESNUG 321 Item 6 ) ---------------------------------------------- [6/8/99]
Subject: ( ESNUG 319 #2 ) Odd Question Marks In My Synthesis Log Files?
> Could somebody help me to understand why I get sometime the question marks
> for a certain register in my synthesis log file. A part of the log file
> looks like this:
>
> ======================================================================
> Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST
> ======================================================================
> cnt_reg | Flip-flop | 8 | Y | N | N | N | N | N | N
> dac_buf_reg | Flip-flop | 1 | - | - | N | N | N | N | N
> data_buf_reg | Flip-flop | 8 | Y | N | N | N | N | N | N
> mod2cnt_reg | Flip-flop | 1 | - | - | N | N | N | N | N
> sum_reg | Flip-flop | 8 | N | N | ? | ? | ? | ? | ?
> ======================================================================
>
> The register bank sum_reg got the question mark for all parameters:
>
> AR, AS, SR, SS, ST
>
> Thanks for any help.
>
> - T.P Nguyen
> Philips Semi/ASG-Microtel Eindhoven, The Netherlands
From: Oren Rubinstein <oren@gigapixel.com>
The question marks mean some of the bits get set and other get cleared.
For instance, if the reset value for an 8 bit register is 01010101.
- Oren Rubinstein
GigaPixel Corp. Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: Oleg Milter <omilter@iil.intel.com>
Hi, John,
The reason of this behavior could be, that you use part of bits in sum
vectors as asynchronous set/reset and part of bits as synchronous set/reset.
If you set hdlin_report_inferred_modules = verbose
the tool will report detailed information for each bit in vector.
- Oleg Milter
Intel Israel Ltd. Haifa, Israel
---- ---- ---- ---- ---- ---- ----
From: George Lambidakis <lambo@sei.com>
John,
The question marks are there because the register in question, "sum_reg" was
not reset to a consistent value. Some of the bits are 1 and some are 0
rather than 8'hff or 8'h00. This is annoying but has been this way for
some time.
- George Lambidakis
Silicon Engineering Inc.
---- ---- ---- ---- ---- ---- ----
From: [ A Synopsys Staff AC ]
John,
The answer to T.P. Nguyen's question is that all of the bits of "sum_reg"
are not initialized the same way. For example, the following code would
cause the elaboration report T. P. is seeing
IF (reset = '0'0 THEN
sum <= "00000001";
ELSIF (clk'event and clk = '1') THEN
sum <= foo;
END IF;
Notice that the elaboration report has an "N" in the BUS column. DC only
considers a register a "BUS" if all the bits are set/reset to the same
value under all conditions. To get more detailed information about each
individual bit set
hdlin_report_inferred_modules = verbose
This will give the set/reset information for each individual bit of each
register.
- [ A Synopsys Staff AC ]
---- ---- ---- ---- ---- ---- ----
From: "T.P. Nguyen" <nguyen@natlab.research.philips.com>
Hi John,
After some deep investigation, the reason I got these question marks is that
the sum_reg was assigned with signals of different sizes. Synopsys reported
question marks for those signals during the elaboration.
- T.P Nguyen
Philips Semi/ASG-Microtel Eindhoven, The Netherlands
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