( ESNUG 321 Item 2 ) ---------------------------------------------- [6/8/99]
From: navin@dalsemi.com (Venkata Navin)
Subject: How Do You Handle Embedded Asynchronous Memory Timing In DC ?
John,
I have the following circuit in my design:
---------
| |--------
|Flop | |
Clk | | ------------ ------------
------- | | | | |
| --------- ---------------- WE | Async. |
| | Combinational|--------| RAM |
------------------------------| Logic | | |
---------------- ------------
WE is the write enable pulse.
As far as I know, DesignTime is going to look at all paths between 2
flip-flops. Now, the RAM library file has all the setup and hold timings
of the address and data of the asynchronous RAM with respect to the write
enable pulse. How does DC try to meet these? Since WE is not defined as
a clock, I think DC would treat the RAM as a combinational element and not
a sequential element. So, would it ignore all the setup and hold
requirements with respect to WE?
Also, the combinational logic generating the WE pulse is don't touched
and instantiated because WE is generated with both edges of the clock.
--------- ---------
| | | |
Clk --------- --------- --------
WE ----------- ------------- ----------
| | | |
----- -----
Is the only way to check this using dynamic simulation? Or would I need to
define WE as a clock? If so, it's not periodic, so how do I go about it?
I guess my question is more general. How do you handle embedded
asynchronous memory timing if the WE is generated by both edges in general?
- Venkata Navin
Dallas Semiconductor
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