( ESNUG 320 Item 15 ) --------------------------------------------- [6/2/99]
Subject: How Do You Model 2 Gbytes Design Mem w/ A 0.5 Gbyte Workstation?
> Does anyone know how to model large amount of memory in Verilog without
> using too much simulation memory space? For instance, if there is
> 1 GBytes of memory in a design how much memory will the memory model
> take during the simulation?
>
> How can the simulation memory requirement be reduced as much as possible
> without degrading simulation performance?
>
> Young K. Choi
From: Edward Arthur <eda@ultranet.com>
Use a sparse memory model.
You can write one via the PLI, use the one supplied with Verilog-XL
or buy them from Denali (http://www.denalisoft.com/) or Synopsys
(http://www.synopsys.com/products/lm/memory/memory.html)
- Edward Arthur
---- ---- ---- ---- ---- ---- ----
From: dave rich <@cadence.com>
Perhaps this should be added to the comp.lang.verilog FAQ.
The Verilog-XL release directory comes with a PLI example called "damem".
I believe other vendors also provide it as a PLI example. It was never
copyrighted. Here are some excerpts from the appnote. System tasks:
$damem_declare
$damem_read
$damem_write
$damem_initb
$damem_inith
The $damem_declare System Task
=============================
The $damem_declare system task declares a memory in your design. It is an
alternative to the use of the reg keyword to declare an array of regs. When
you use the $damem_declare system task to declare a memory in a design,
Verilog-XL does not allocate memory space in your workstation for that
memory in your design until you enter another system task for dynamically
allocated memories ($damem_write, $damem_initb, or $damem_inith) that writes
data to that memory in your design. When Verilog-XL allocates this memory
space, it only allocates enough memory space to hold the data written to
that memory in your design.
$damem_declare(name_of_memory,bit_from,bit_to, addr_from, addr_to);
$damem_write (name_of_memory,addr,value);
$damem_read(name_of_memory,addr,register);
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