( ESNUG 320 Item 11 ) --------------------------------------------- [6/2/99]
Subject: Useful Web Sites If You're Designing High Speed FPGA Multipliers
> I was wondering if anyone can refer me to some information about designing
> an 8-bit by 4-bit unsigned multiplier and an 8-bit by 4-bit signed
> multiplier that will perform at high clock speeds and have efficient usage
> of CLBs on the Xilinx Virtex FPGA.
>
> - Allen Tung
> Visicom Labs San Diego, CA
From: brian@esperan.com ( Brian Dickinson )
For some info on different FPGA multiplier architectures, take a look at:
http://users.ids.net/~randraka/multipli.htm
- Brian Dickinson
Esperan
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From: "James E. Stine, Jr." <jes6@eecs.lehigh.edu>
There are a variety of different tools and programs for VHDL generation of
computer arithmetic at http://www.eecs.lehigh.edu/~caar/toolspg.html. These
tools can be obtained free of charge by way of written request. They
include Perl generation of structural Dadda (optimized Wallace) multipliers
and Array multipliers which can easily be transformed into signed
multiplication using techniques such as the ones described by Baugh and
Wooley. Take care.
- James Stine
LeHigh University
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From: mcgett@xilinx.com (Ed Mcgettigan)
The Xilinx IP Center has a number of multipliers available for Virtex.
http://www.xilinx.com/ipcenter/reference_designs/index.htm#Math
- Ed Mcgettigan
Xilinx
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