( ESNUG 320 Item 8 ) ---------------------------------------------- [6/2/99]
Subject: ( ESNUG 316 #11 ) Verilog-XL Back-annotation Slow Compared To VCS
> Has anyone found that for a given testbench, back-annotation an sdf file
> for a gate-level simulation in Verilog-XL takes MUCH longer than it does
> with VCS? (3-4 hours vs. 4 minutes respectively for one of my test
> benches). What's the reason for this? How does each tool perform back-
> annotation?
>
> At first, I thought that VCS wasn't performing back-annotation, but after
> throwing some deliberate "errors" in the netlist at VCS, it detected them.
>
> I changed the module type from a low-drive gate to a high-drive gate. I
> changed the instance name to something non-existent in the sdf file. Both
> changes were flagged by VCS. Can anyone offer any explanations?
>
> I'm using VCS v5.0 and Verilog v2.6.
>
> - Alfred Cheung
> Nortel Networks Ottawa, Ontario
From: soconnor@pico.apple.com (Stephen O'Connor)
This matches my experience -- the times you note sound right -- annotation
in VCS is very very fast. Coming from XL sims, the question for a long time
was "Why is XL annotation so slow!" It's a big delay at a point when the
schedule is usually at its most pressing.
However, we have occasionally seen differences with gate sims under both,
so keeping both options open, as it seems you can, might be wise.
- Stephen O'Connor
Apple Computer
> You may be using the compiled SDF feature of VCS, which may be default
> now. In that case, the SDF file is read at compile time rather than at
> run time.
>
> - Ashutosh Varma
> Axis Systems Sunnyvale, CA
From: srini@natlab.research.philips.com (Srini Venkataramanan)
John,
If Asuthosh is correct, then NC-Verilog handles the SDF back-annotation in
a similar (compiled) manner. May be Alfred can try that as an option.
- Srini Venkataramanan, M.Tech (srini)
Philips Research Laboratories Eindhoven, The Netherlands
|
|
