( ESNUG 319 Item 12 ) -------------------------------------------- [5/26/99]
Subject: ( ESNUG 318 #10 ) Want DC To Remove Tied-off/'Dead' Flip-flops
> I am having difficulty getting Design Compiler to remove flip-flops that
> are tied off to a useless state. The specific example I am looking at is
> a d-type flip-flop with an asynchronous clear. It's D input is tied to
> '0'. The CLR input comes from other logic. So only 0's can be clocked in
> to this flop, and it can be cleared to set it to '0'. There is no way to
> set it to '1'.
> ---------
> '0' ----| D Q |---- Output
> | |
> CLK ----|> |
> Reset -----------| RST |
> ---------
>
> It seems to me that Design Compiler should optimize this dead flip-flop
> away and replace it with a tie-off to '0', which should then allow
> logic on the output side of the logic to be further optimized away.
> However, in my experience, this is not the case. The commands: compile,
> compile -boundary, and compile -in_place will not do what I want it to
> do. This configuration is not exactly the same as a tie-off since the
> flop could possibly power on in the '1' state, but I don't think this is
> a good enough reason not to allow the above optimization. Has anyone had
> any success with this, or know a better reason why this should not be
> optimized away?
>
> - John Patty
> Ericsson Research Triangle Park, NC
From: Gzim Derti <gderti@intrinsix.com>
Hi John,
Just my $0.000002 worth on this...
The issue that I see with the way that the gates are generated have to do
with the timing around the reset vs. clk interface. I'm not sure, but I'd
bet money that since DC sees a timing arc between reset and CLK, i.e. if
reset changes state too close to when clock occurrs possibly causing a
metastable condition, that DC "thinks" that this is an important issue
to model in simulation so the Flop stays as-is.
While for a long time, at slower clock freq's, many designers, myself
included, have seen the transition out of reset as a "system level" issue
when things start speeding up you've got to try and create "synchronous"
transitions on your reset signal or things go to "hell-in-a-hand-basket",
so to speak.
Anyway, it's early AM for me right now and I could be all wet, but that's
my best guess into the "mind of DC".
- Gzim Derti
Intrinsix Corp. Rochester, NY
---- ---- ---- ---- ---- ---- ----
From: Andrew Maccormack <andrewm@bristol.st.com>
John,
We use a pretty similar circuit quite frequently in our designs here:
--------------- (Q feeds back to D)
| --------- |
----| D Q |---- Output
| |
CLK ----|> |
Reset -----------| RST |
---------
Why? Well, we call these circuits "testable ties". If you have a real
gnd/vdd tie in your circuit, it can ruin your fault coverage. Since our
ATPG target is 99.7% coverage in all standard cell designs, we do not
want to take that hit. The above circuit offers the same functionality
in functional mode, but in parallel scan mode, we can shift a '1' into
the register no problem and therefore have complete controllability and
therefore fault coverage of that output.
Maybe that's why those FFs are in there and this user should consider what
removing them would do to his fault coverage.
- Andrew R MacCormack
STMicroelectronics UK
---- ---- ---- ---- ---- ---- ----
From: William Liao <wliao@mmcnet.com>
Hi, John,
I've noticed the problem John Patty described for several years now, and
it's only a subset of the real problem, which is Design Compiler never
removes storage elements. I've tried connecting set, reset, clock, or data
to force FFs or latches to constant values, and DC always kept them in
the design.
I asked a Synopsys engineer about this problem once (at SNUG'97 I think).
He suggested me to file a bug report. I never followed up. Perhaps I
should have.
- William Liao
MMC Networks
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