( ESNUG 319 Item 4 ) --------------------------------------------- [5/26/99]
From: Robert_W_Smith@res.raytheon.com ( Robert Smith )
Subject: Extremely Wild Lucent ORCA Timing Estimates W/ FPGA Compiler 98.02
John,
I have a general FPGA question I would like to put to the ESNUG community.
We have been using FPGA Compiler 98.02 (not FPGA Express) to design mostly
Lucent ORCA 2C and 3C/T FPGAs. Our impression has been that the timing in
the provided Synopsys FPGA libraries is not too accurate, or at least
doesn't agree with the FPGA tools -- the Synopsys timing reports seem
to vary from wildly pessimistic to wildly optimistic compared to what we
get when we route. Consequently, we have been using Synopsys mainly as a
plain synthesis engine and doing our optimizations, pipelining, etc. from
the place and route results. Needless to say, we would love to optimize a
lot sooner in the process, as long as Synopsys can reflect the actual
results we can get when we route.
So what is the experience in ESNUGland? Are the Synopsys FPGA libraries
accurate enough to trust Synopsys' timing info? Should we be making better
use of Synopsys up front to reduce our FPGA place and route iterations? Do
other FPGA companies provide more accurate libraries than Lucent? Is FPGA
Express or the coming FPGA Compiler II better at this?
BTW, one trick we have been using is to examine the verbose timing report
for the mapped circuit, where all routing delays are set to zero. Not only
does this save having to run place and route, but it better highlights your
true logic bottlenecks. If the router tackles tough logic first, then the
paths which end up not meeting timing won't be the ones really causing your
problem.
- Bob Smith
Raytheon Systems Company Marlboro, MA
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