( ESNUG 318 Item 6 ) --------------------------------------------- [5/21/99]
Subject: Grumpy Collett & Other Reader Response To The SNUG'99 Trip Report
> Bad idea. It not only leaves the Synopsys "infrastructural problems"
> unfixable by customers, it also recklessly leaves Synopsys management
> vulnerable to their own soothsaying Marketeers, yes-men, and Rasputins.
> And many times these weaselly flatterers are more caught up in their own
> Palace Intrigues than presenting the Real Truths their customers are
> facing. Is a VSS (VHDL) Marketing Manager ever going to say "Hey, let's
> dump our internally developed VHDL simulator, buy Chronologic, and sell
> the world's fastest Verilog simulator instead!"? (And you tell me: would
> *you* bet *your* livelihood on a Collett Market Forecast???)
From: Ron Collett <ronc@collett.com>
John, is this your personal editorial?
It would appear so.
What I find so amusing about your attempts to criticize our firm is that 5
years ago when you and I met for the first and only time (in San Diego),
your lack of knowledge on design methodology astounded me. As I recall, you
couldn't understand why logical and physical design would ever have to be
integrated together. I tried to explain to you about the notion of
interconnect-delay dominating performance, but you resisted and were rather
dumbfounded by the concept. This is why I had no interest in sitting down
with you again after that meeting. I just didn't see any point to it. My
suspicions about your limited knowledge were confirmed when I saw you
moderate the CEO Executive Panel at a later DAC.
However, I'm a reasonable guy, and I'm willing to give you a second chance,
because perhaps you have gained lots of insight into what what kind of
design methodologies will be needed in the future -- I hope so for your
client's sake. What do you think the chip design methodology will look like
4 years from now? What are the issues? What will the solution space look
like? What does the design environment look like? Perhaps if you have some
time you should publish some of your thoughts on this. Please be specific.
Do you have the "professional courtesy" to publish this reply to your ESNUG
subscribers?
> "After my first experience hearing Ron Collet's VHDL presentation, I
> was always very skeptical of his market analysis. In 1996, it hit
> directly in my realm when he avoided the VHDL-versus-Verilog topic
> and began to harp on the demise of the UNIX workstation platform
> in favor of Windows NT."
>
> - Clay Degenhardt of Systems Science in ESNUG 286
John,
I don't mind a healthy debate, in fact I enjoy it, as long as it is grounded
in factual information -- debates surrounded by exaggerations, distortions,
statements captured out of context, and missing information are not worth my
time. I'm sure their not worth yours either.
It seems this guy Clay chooses to leave out relevant information when
characterizing what I say. In short, with regard to the NT vs. Unix
debate -- one of the assumptions in the model which I have presented many,
many times was that Microsoft would need to execute, which meant for example
that NT would have to reach parity with Unix's functional, performance and
reliability capabilities, and Microsoft would have to significantly ease
the switching costs for customers, etc.; in the absence of this, Unix
would continue to prevail. Thus far from what I've seen, Microsoft has not
been at all serious about the EDA market -- it's not surprising, given its
size. This is in spite of the fact that Microsoft did make a lot of noise
several years ago about NT for the EDA market -- e.g. coming to DAC, holding
big press conferences, rounding up EDA vendors to endorse NT, etc. It has
not added up to a whole lot. So when Clay talks about what I said, he omits
quite a bit. Moreover, from what I understand, Clay was an MIS guy at
Zycad -- not at all involved in any strategy decision-making. He sat in
once or twice on a company-wide, general presentation that I gave. He was
not at all privy to the details of the analyses, etc. I don't fault him for
what he doesn't know, but he should be a bit more conscientious before
making statements that exaggerate and omit relevant facts.
- Ron Collett
Collett International Santa Clara, CA
[ Editor's Note: Ron, before I address your questions, it's very important
to understand that we live in two different worlds. My world is deep in
the details of chip design in the *present*. It's t-shirts & cubicals,
workstations, PCs, vending machine fare for lunch, inferring 3:1 MUXes,
Test Compiler won't take parallel buffered clock trees unless you set the
variable test_allow_clock_reconvergence = true, and wondering if I should
take Synopsys Chip Architect classes for my next project. Your world is
the lala-land of what *might* be in chip design. It's suits & ties, slick
powerpoint slides, offices with personal receptionists, 'power' lunches
with CEOs in swank restaurants and snooty waiters, and wondering what
the Wall Street Journal will write next. I went to a state univeristy
and studied engineering. You went to Stanford and studied law. I watch
the TV show 'COPS' to see if any of my family is in trouble. You watch
the PBS 'Nightly Business Report' to see how your portfolio is doing. My
first traumatic life experience involved a sheriff's deputy leveling a
shotgun at my head on a dark winter night in Vermont. Your first
traumatic life experience involved maxing out daddy's credit card while
in Saks Fifth Avenue. Ron, our worlds are very, _VERY_ different.
Casting these sarcastic personal aspersions asides, we really do live in
very different worlds. You do financial 'stuff' and it's OK with your
Armani buddies to make wild predictions/projections that don't pan out.
I can remember when you wrote years ago that engineers were dying to
move to PCs so they can connect their EDA output to Excel spreadsheets.
Or that chip design was going to transform into just software coding with
cheap embedded processors mimicking chip functions. So what if these
guesses turned out to be completely wrong? The Armani crowd expects and
accepts wildly misleading prognostications. My world is firmly entrenched
in the gritty details of *here* and *now*. I'm paid to solve problems
*now*. Not in a year, not in six months, but *now*. And if I'm wrong, I
catch *loud* and *immediate* hell for it. Five years ago, my customers
and readers weren't talking about interconnect delay dominating anything,
hence I devoted zero personal effort to it. (In fact, I was busy learning
VHDL at the time, if I remember accurately, and many people were wondering
if they should switch to it -- hence my Verilog vs. VHDL design contest.)
It's only in the past year or so that I've had clients worried about a
chip's porosity or its gate-to-net ratio. So it's *now* I start paying
attention to P&R, Manhattan distances, & aspect ratios. I'm the ghost of
Christmas Present; you're the ghost of Possible Christmasses Yet To Come.
While you sell market forecasts and tweak powerpoint slides, I sweat the
details on chips that *actually must work* when they come back from the
fab in eight weeks. For me, far off into the future stops right at the
beginning of my next project.
Concerning your comments about Clay, I can't discredit his view as lightly
as you do. He *knows* about UNIX and Windows because he's hip deep in the
stuff every day. I respect his opinions on this far more than any windbag
who can't diff between grep and sort -u. So Clay didn't sit in on the
bigwig meetings. BFD. And, yea, I've seen my share of bad predictions
made by too-close-to-the-details engineers, too. But it doesn't mean he's
anywhere near as clueless as you're portraying him, Ron. Sheesh! - John ]
---- ---- ---- ---- ---- ---- ----
From: Austin Franklin <austin@darkroom.com>
Hi John,
Thank you for your 'impressions' on SNUG'99.
Since I am not a 'registered' Synopsys user, I can't get at the papers.
Would you be so kind as to email them to me or let me know how I go about
acquiring them?
(MA2) Tutorial of FPGA Compiler II
(MC3) Large FPGAs, FPGA Express
"FPGA Express Coding Techniques" by David Nye of Xilinx.
Regards,
- Austin Franklin
Darkroom
---- ---- ---- ---- ---- ---- ----
From: zyang@avanticorp.com
Hi, John
I am impressed by your ESNUG report.
By the way, do you have the numbers of IP and IP tool market today and 3/5
years projected?
- Z Yang
Avant!
---- ---- ---- ---- ---- ---- ----
> "Wireload models are like the weather. Many people talk about them,
> but not many people *do* anything about them! ..."
>
> - the abstract to Steve Golson's 1st place SNUG'99 paper
> titled "Resistance is Futile! Building Better Wireload Models"
From: Don Reid <donr@hpcvcdo.cv.hp.com>
John,
As things are now it is difficult to even experiment with anything
else. Until DC either supports some alternate model or provides hooks
to connect user defined load calculation, we are stuck with wire load
models.
- Don Reid
Hewlett Packard Corvallis, OR
---- ---- ---- ---- ---- ---- ----
> "I think Synopsys is facing some real challenges next year. I've got
> Design Compiler blowing out on my current design. As a user and a
> stockholder I'm concerned. Design Compiler is using too much memory."
>
> - chip designer and consultant Kurt Baty at Aart's speech
>
> "I second Kurt's problems. We, at HP, are seeing this, too."
>
> - an anon voice in the crowd at Aart's speech
From: "Ann Steffora" <asteffora@cahners.com>
John,
Do you think Avant! has a strong chance of being successful with their
methodology, which they are not shy about saying it is specifically not
based on synthesis? (I'm till trying to figure out why Avant! would have
sent out mousetraps and cheese to customers.... that's just plain weird!)
- Ann Steffora
Electronic News
---- ---- ---- ---- ---- ---- ----
From: Adrian Dunn <adunn@domosys.com>
John,
Let me congratulate you on a report that was both very informative, as well
as quite entertaining. Out company partnered with Cadence's Design Services
group on a past ASIC project, and as such, use many of Cadence's (and now
Ambit's) tools. Do you know of a similar conference for Cadence tool users,
as well as a user/guru who publishes such lucid summaries?
- Adrian Dunn, Software Analyst
Domosys Corporation Sainte-Foy (Quebec) Canada
---- ---- ---- ---- ---- ---- ----
From: Philip Freidin <fliptron@netcom.com>
I can't help but wonder how functional you are today, given that you must
be rolling around the floor laughing yourself silly.
I refer, of course, to the column by your favorite nostradamus (Ron Collett)
on page 53 of the April 26th EETimes ("It's Finally Jack's House"), and the
front page story of the following week's EETimes where Jack Harding is
ousted as CEO of Cadence.
- Philip Freidin
Fliptronics
[ Editor's Note: Believe me, Philip, I wasn't the only one laughing at that
one! I got 6 gushing phone calls and 4 e-mails when it happened. This
might explain Ron's grumpy letters (see above) from that week. - John ]
---- ---- ---- ---- ---- ---- ----
> The foundries are also backing PrimeTime with 6 of them (IBM, LSI, TI,
> NEC, Fujitsu, Toshiba, and Samsung) publically accepting design timing
> sign-off with PrimeTime."
From: reynoldk@us.ibm.com (Karla Reynolds)
John,
I need to correct this comment about PrimeTime you made in your SNUG'99
dissertation. Timing sign-off on ASIC designs manufactured here at IBM, is
done ONLY with Einstimer, our internally developed static timing tool.
PrimeTime, currently and for the foreseeable future, is not qualified for
timing sign-off.
- Karla Reynolds
Mgr. Timing and Synthesis Department
IBM Microelectronics Essex Junction, Vermont
[ Editor's Note: Karla, doing a web search, I found press releases from
each of those companies endorsing PrimeTime except IBM. For IBM, at
http://www.chips.ibm.com/products/asics/methodology/design_flow.html
clearly has PrimeTime being supported by IBM. My appologies if this
data is wrong; I assumed IBM's own web site was accurate. - John ]
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